NO. DE PÁGINAS: 594

CONTENIDO:

VHDL for Programmable Logic is appropriate for courses in VHDL, advanced logic design, and ASIC design, as well as for professional engineers and graduate students interested in updating their design methodologies to include both VHDL and programmable logic devices. The objectives of this book are to equip the reader with:

• the skills to write VHDL code that can be synthesized to efficient logic circuits,
• an understanding of the VHDL and programmable logic design process from design description through synthesis, placement, and routing, to the creation of test benches for design verification,
• a knowledge of design trade-offs that can be made, and
• a toolbox of techniques that can be modified and used to solve unique design problems.

To achieve these objectives, the book covers VHDL by:

• emphasizing real-world examples rather than abstract theories,
• including design topics súch as state machine design, area versus performance tradeoffs, parameterized components, hierarchy and libraries, pipelining and resource sharing,
• using numerous examples reduced through synthesis to logic gates,
• demonstrating options for synthesizing, fitting, placing, and routing logic circuits within CPLDs and FPGAs,
• introducing breakout exercises that reinforce design topics and quickly bring the reader up to speed with using the included Warp software, and
• including over 80 design files on the enclosed CD-ROM, some for use with the problem sets and hands-on experience with synthesizing, fitting, placing,and routing.