Z8 Opcode Listing Zilog Z8 Microcontroller Instruction Set. --------------------------------------------------- src = SOURCE OPERAND dst = DESTINATION OPERAND cc = CONDITION CODE --------------------------------------------------- Load Instructions: --------------------------------------------------- CLR dst CLEAR dst <= 0 LD dst,src LOAD dst <= src LDC dst,src LOAD CONSTANT dst <= src LDE dst,src LOAD EXTERNAL dst <= src POP dst POP dst FROM STACK PUSH src PUSH src INTO STACK --------------------------------------------------- --------------------------------------------------- Arithmetic Instructions: --------------------------------------------------- ADC dst,src ADD WITH CARRY ADD dst,src ADD CP dst,src COMPARE DA dst DECIMAL ADJUST DEC dst DECREMENT DECW dst DECREMENT WORD INC dst INCREMENT INCW dst INCREMENT WORD SBC dst,src SUBTRACT WITH CARRY SUB dst,src SUBTRACT --------------------------------------------------- --------------------------------------------------- Logical Instructions: --------------------------------------------------- AND dst,src LOGICAL AND COM dst COMPLEMENT oposite bits OR dst,src LOGICAL OR XOR dst,src EXCLUSIVEOR --------------------------------------------------- --------------------------------------------------- Program Control Instructions: --------------------------------------------------- CALL dst CALL SUB ROUTINE DJNZ dst,src DEC JUMP NON-ZERO label,counter IRET INTERRUPT RETURN JP cc,dst JUMP JR cc,dst JUMP RELATIVE RET RETURN FROM SUB ROUTINE --------------------------------------------------- --------------------------------------------------- Bit Manipulation Instructions: --------------------------------------------------- TCM dst,src TEST COMPLEMENT MASK test 1 TM dst,src TEST MASK test 0 AND dst,src BIT CLEAR with 0 in src OR dst,src BIT SET with 1 in src XOR dst,src BIT COMPLEMENT with 1 in src --------------------------------------------------- --------------------------------------------------- Block Transfer Instructions: --------------------------------------------------- LDCI dst,src LOAD CONSTANT AUTOINCREMENT LDEI dst,src LOAD EXTERNAL AUTOINCREMENT --------------------------------------------------- --------------------------------------------------- Rotate and Shift Instructions: --------------------------------------------------- RL dst ROTATE LEFT RLC dst ROTATE LEFT THROUGH CARRY RR dst ROTATE RIGHT RRC dst ROTATE RIGHT THROUGH CARRY SRA dst SHIFT RIGHT ARITHMETIC SWAP dst SWAP NIBBLES --------------------------------------------------- --------------------------------------------------- CPU Control Instructions: --------------------------------------------------- CCF COMPLEMENT CARRY FLAG DI DISABLE INTERRUPS EI ENABLE INTERRUPS HALT HALT NOP NO OPERATION RCF RESET CARRY FLAG SCF SET CARRY FLAG SRP src SET REG POINTER load with src STOP STOP WDH WATCH DOG ENABLE DURING HALT WDT WATCH DOG ENABLE OR REFRESH TIMER --------------------------------------------------- ------------------------------------ FLAG DEFINITIONS ------------------------------------ C CARRY Z ZERO S SIGN V OVERFLOW D DECIMAL ADJUST H HALF CARRY ------------------------------------ ---------------------------------------------------------------- CONDITION CODES: MNEMONIC DEFINITION FLAG SETTINGS ---------------------------------------------------------------- F ALWAYS FALSE - (blank) ALWAYS TRUE - C CARRY C=1 NC NO CARRY C=0 ---------------------------------------------------------------- Z ZERO Z=1 NZ NON ZERO Z=0 PL PLUS S=0 MI MINUS S=1 ---------------------------------------------------------------- OV OVERFLOW V=1 NOV NO OVERFLOW V=0 EQ EQUAL Z=1 NE NOT EQUAL Z=0 ---------------------------------------------------------------- GE GREATER THAN OR EQUAL (S XOR V)=0 LT LESS THAN (S XOR V)=1 GT GREATER THAN (Z OR (S XOR V))=0 LE LESS THAN OR EQUAL (Z OR (S XOR V))=1 ---------------------------------------------------------------- UGE UNSIGNED GREATER THAN OR EQUAL C=0 ULT UNSIGNED LESS THAN C=1 UGT UNSIGNED GREATER THAN (C=0 AND Z=0)=1 ULE UNSIGNED LESS THAN OR EQUAL (C OR Z)=1 ----------------------------------------------------------------