













VeriWelltm User's Guide 2.0

























Wellspring Solutions, Inc.

P.O. Box 150

Sutton, MA 01590

(508) 865-7271 - BBS/Fax: (508) 865-1113

info@wellspring.com





June, 1995

Copyright 1995 Wellspring Solutions, Inc.

ALL RIGHTS RESERVED



NOTICE

Wellspring Solutions Inc. has prepared this manual for use by
Wellspring Solutions personnel, licensees, and customers.  The
information contained herein is the property of Wellspring
Solutions, Inc. and is covered by copyright.  The software
described in this manual and the manual itself are furnished
under a software license agreement and may be used only in
accordance with the terms of such license.

The information contained in this manual is subject to change
without notice and should not be construed as a commitment by
Wellspring Solutions.  Wellspring Solutions assumes no
responsibility for any errors that may appear in this document.

VeriWell, VeriWell 2.0, VeriWell Preference, and WellspringWaves
are trademarks of Wellspring Solutions, Inc.

Verilog and Verilog-XL are registered trademarks of Cadence
Design Systems, Inc.

Synopsys and HDL Compiler are registered trademarks of Synopsys,
Inc.

Macintosh and System 7 are trademarks of Apple Computer, Inc.

SunOS is a trademark and Sparc is a registered trademark of Sun
Microsystems, Inc.

UNIX is a trademark of AT&T.

Microsoft, MS-DOS, Win32, and Win32s are registered trademarks
and Windows is a trademark of Microsoft Corp.

Software License Agreement and Warranty

Wellspring Solutions, Inc.'s complete Software License
Agreement, its conditions, terms, warranty and limitations, as
they relate to the purchase and use of Wellspring Solutions'
software products, is found at the end of this document. 
Customers are expected to read this agreement before breaking
the seal on the package containing the software.

References to Features and Products

This document may contain references to products, functions, and
capabilities not yet announced or available.  If you have
questions about the suitability of this product for specific
applications and the availability of features and functions,
please contact Wellspring Solutions.

References to Other Vendors' Products

This document may refer to products and features of vendors
other than Wellspring Solutions.  Where such references exist,
every effort has been made to ensure the validity of the
reference at the time of publication.  Wellspring Solutions,
Inc. makes no warranty of any kind as to the performance or
features of another vendor's products.

Shareware

This document may reference software known as shareware. 
Shareware is a concept where software is obtained on a trial
basis.  Payment is made to the author after it is determined
that the software is useful and will continue to be used.  Where
such references exist, you are encouraged to register the
shareware with the creator if you decide to use it.



Printed in the USA.

Copyright  1995 Wellspring Solutions, Inc.

All Rights Reserved.

Part I:  Introduction 	 

Chapter 1:  Getting Acquainted 	  

Checking Your Package 	1 - 1 

Readme File 	1 - 1 

VeriWell/Free and Copy Protection 	1 - 2 

Registering VeriWell 	1 - 2 

Customer Support 	1 - 3 

Bug Reports 	1 - 3 

Ordering Wellspring Solutions' Products 	1 - 3 

Info-VeriWell Mailing List 	1 - 4 

Receiving Updates 	1 - 4 

Bulletin Board System (BBS) 	1 - 4 

File Transfer Protocol (FTP) 	1 - 6 

Electronic Mail (Email) 	1 - 6 

Regular Mail 	1 - 7 

Recommended Publications 	1 - 7 

Open Verilog International (OVI) 	1 - 8 

Chapter 2:  The VeriWell User's Guide 	  

How to Use This Manual 	2 - 1 

Intended Audience 	2 - 1 

Scope of Manual 	2 - 1 

Manual Organization 	2 - 2 

VeriWell Release Notes  	2 - 3 

Chapter 3:  About VeriWell 	  

Overview of Verilog HDL 	3 - 1 

About VeriWell 	3 - 2 

What's New in VeriWell, Version 2.0 	3 - 3 

Part II:  VeriWell 	 

Chapter 1:  Using VeriWell 	  

Introduction 	1 - 1 

Invoking VeriWell 	1 - 1 

Command Files 	1 - 2 

Command Interaction 	1 - 3 

More on Interactive Commands 	1 - 4 

Input files 	1 - 5 

Debugging Techniques 	1 - 5 

Interactive Commands 	1 - 6 

Command Line Options 	1 - 7 

Predefined Plus Options 	1 - 8 

Compilation 	1 - 10 

Chapter 2:  VeriWell Feature List 	  

Data Types 	2 - 1 

Operands (Conforms to Expression Bit-Length Rules) 	2 - 1 

Operators 	2 - 2 

Built-in Primitives 	2 - 2 

User-Defined Primitives 	2 - 2 

Statements 	2 - 2 

Hierarchical Structures 	2 - 3 

Specify Blocks 	2 - 3 

System Tasks and Functions 	2 - 3 

Command Line Options 	2 - 3 

Compiler Directives 	2 - 4 

Predefined Plus Options 	2 - 4 

Interactive Commands 	2 - 4 

Limitation Summary 	2 - 4 

Chapter 3:  OVI LRM Cross-Reference 	  

1  Introduction 	3 - 1 

2  Lexical Conventions 	3 - 1 

3  Data Types 	3 - 1 

4  Expressions 	3 - 2 

5  Assignments 	3 - 2 

6  Gate and Switch Level Modeling 	3 - 2 

7  User-Defined Primitives (UDPs) 	3 - 3 

8  Behavioral Modeling 	3 - 3 

9  Tasks and Functions 	3 - 4 

10 Disabling of Named Blocks and Tasks 	3 - 4 

11 Procedural Continuous Assignments 	3 - 4 

12 Hierarchical Structures 	3 - 4 

13 Specify Blocks 	3 - 4 

A  Formal Syntax Definition 	3 - 5 

B  System Tasks and Functions 	3 - 5 

C  Compiler Directives 	3 - 5 

D  List of System Task and System Function Keywords 	3 - 5 

E  List of Compiler Directive Keywords 	3 - 7 

Chapter 4:  VeriWell Implementation Notes 	  

Port Collapsing 	4 - 1 

Port Connections of Different Net Types 	4 - 1 

Pullup/Pulldown Workaround  	4 - 1 

Using Trace 	4 - 2 

Predefined Macro "__VERIWELL__" 	4 - 2 

Simulation Statistics 	4 - 2 

Displaying Location of Last Value Change 	4 - 3 

User Interrupt 	4 - 3 

Chapter 5:  Implementation Differences from Verilog-XL 	  

Introduction 	5 - 1 

Event Ordering 	5 - 1 

Module Ports and Port Collapsing 	5 - 1 

Control Expressions Limited to 32 Bits 	5 - 2 

$Monitor 	5 - 2 

Scoping 	5 - 2 

Key File 	5 - 2 

Part III:  VeriWell Preference Modules 	 

Chapter 1:  Introduction 	  

Modular Architecture 	1 - 1 

Chapter 2:  Gate-level and Timing Preference 	  

User-Defined Primitives and Memory Usage 	2 - 1 

Specify Blocks 	2 - 1 

Chapter 3:  WellspringWaves Preference 	  

Introduction 	3 - 1 

WellspringWaves Syntax 	3 - 1 

What is Included 	3 - 2 

Installing WellspringWaves 	3 - 2 

Using WellspringWaves for the First Time 	3 - 3 

VeriWell with WellspringWaves 	3 - 3 

Using WellspringWaves 	3 - 3 

Part IV:  Your VeriWell Environment 	 

Chapter 1:  VeriWell for DOS 	  

Introduction 	1 - 1 

Before You Begin 	1 - 1 

System Requirements 	1 - 1 

What is Included 	1 - 2 

VeriWell for DOS Installation Summary 	1 - 2 

Installing VeriWell for DOS 	1 - 3 

About the DOS Extender 	1 - 5 

DOS Considerations 	1 - 6 

Memory 	1 - 6 

Scrolling and Shelling 	1 - 6 

Control-D to Exit 	1 - 6 

43 and 50 Lines per Screen 	1 - 7 

Control-C and Control-Break 	1 - 7 

Positioning of Caps Lock and Control Keys 	1 - 7 

Line Terminators 	1 - 7 

Simulation Time Information 	1 - 7 

Chapter 2:  VeriWell for Sparc 	  

Overview 	2 - 1 

System Requirements 	2 - 1 

What is Included 	2 - 1 

Installing VeriWell for Sparc 	2 - 1 

Sparc/UNIX Considerations 	2 - 2 

Line Terminators 	2 - 2 

Passwords 	2 - 2 

Chapter 3:  VeriWell for Macintosh and Windows 	  

Overview 	3 - 1 

Before You Begin 	3 - 1 

System Requirements for Macintosh 	3 - 1 

System Requirements for Windows 	3 - 1 

What is Included 	3 - 2 

Installing VeriWell for Macintosh 	3 - 2 

VeriWell for Windows Installation Summary 	3 - 2 

Installing VeriWell for Windows 	3 - 3 

Quick Start 	3 - 7 

Working with Projects 	3 - 7 

Creating a New Project 	3 - 8 

Opening an Existing Project 	3 - 8 

Closing Projects 	3 - 8 

Adding Files to Projects 	3 - 8 

Removing Files from the Project 	3 - 9 

Changing Project Preferences 	3 - 9 

Editing Files 	3 - 10 

Creating and Opening Files 	3 - 10 

Editing a File 	3 - 11 

Typing Text 	3 - 11 

Undoing Changes to a File 	3 - 11 

Selecting Words and Lines 	3 - 11 

Indenting 	3 - 12 

Shifting Blocks Right and Left 	3 - 12 

Changing Editor Preferences 	3 - 12 

Moving Around a File 	3 - 12 

Saving a File 	3 - 14 

Searching and Replacing Text 	3 - 14 

Printing Files 	3 - 15 

Closing a File 	3 - 15 

VeriWell Console Window 	3 - 16 

Opening 	3 - 16 

Resizing 	3 - 16 

Entering Commands 	3 - 16 

Console Output 	3 - 17 

Searching 	3 - 17 

Printing 	3 - 17 

Running a Simulation 	3 - 18 

Changing Console Preferences 	3 - 18 

Closing 	3 - 18 

Search List Window 	3 - 19 

Opening 	3 - 19 

Adding New Paths 	3 - 19 

Folder Search Order 	3 - 19 

Changing the Search List Order 	3 - 20 

Absolute versus Relative References 	3 - 20 

Removing Paths 	3 - 20 

Resizing 	3 - 21 

Closing 	3 - 21 

Veriwell Menus 	3 - 21 

Apple (VeriWell for Macintosh) 	3 - 21 

File 	3 - 21 

Edit 	3 - 22 

Search 	3 - 24 

Project 	3 - 24 

Windows (VeriWell for Macintosh) 	3 - 26 

Window (VeriWell for Windows) 	3 - 26 

Help (VeriWell for Windows) 	3 - 27 

Command Shortcuts for Macintosh and Windows 	3 - 28 

Wellspring Solutions, Inc. Software License Agreement 	  





Part I:		Introduction

Chapter 1:	Getting Acquainted

Chapter 2:	The VeriWell User's Guide

Chapter 3:	About VeriWellChapter 1:	Getting Acquainted

This chapter provides VeriWell users with important and useful
information about Wellspring Solutions, Inc., their products and
services.

Checking Your Package

Take time to check the contents of your VeriWell 2.0 package. 
As a new VeriWell customer your package contains the following
(exceptions are noted by a '*'):

 3-ring binder

 Documentation

VeriWell User's Guide 2.0

Release Notes (* A set of Notes may be included if enhancements
have been documented since the VeriWell User Guide 2.0 print
date.  Reference Part I, Chapter 2.) 

 Polybag containing,

Software:  One or more 3.5" floppy disks depending on what
software you ordered (* Your package may not contain disks if
you received your software electronically.)

Registration card

Hardlock key (* Some VeriWell versions do not ship with a
hardlock key.)

 3-ring plastic sleeve to house disk(s) and hardlock key

 VeriWell 2.0 Feature List

 Customer letter

Readme File

Users should read the 'Readme' file found on the software media
included with the product package to reference the latest
information that may not have been available at the time the
manual was published.

VeriWell/Free and Copy Protection

Most versions of VeriWell are copy-protected in some way. 
VeriWell for DOS, for example, requires that a hardware key be
plugged into the printer port of the PC.  VeriWell for Sparc
requires a special code be provided on the command line.  Unlike
most copy protected programs, however, the absence of the
protection mechanism does not cause VeriWell to stop working.

If the copy protection mechanism is missing, VeriWell will run
anyway, although the size of the source module is limited.  This
mode is referred to as VeriWell/Free.

VeriWell/Free is VeriWell without the copy protection.  There is
one executable (for each platform).  With the copy protection
enabled, it runs unlimited-sized models and the Preference
modules owned by the user.  (See Part III for a description of
VeriWell Preference Modules.)

Without the copy protection, VeriWell runs about 1000 lines of
source code, not including comments and whitespace, and with
most Preference functionality enabled.  The VeriWell executable
(VeriWell/Free) is freely distributable.  It is available from
public FTP sites and bulletin boards.   (Instructions for
downloading are provided later in this chapter.)

The free version can be used for small designs, to learn
Verilog, or to evaluate VeriWell.  It is not shareware -- there
is never any obligation to upgrade to the registered version.

For registered users, the version of VeriWell that is posted at
the FTP and BBS sites represents the latest version of the
software and can be downloaded periodically and used as an
update.

Registering VeriWell

We advise customers to register their software by filling out
the pre-addressed and pre-stamped Registration Card included in
the product package and mailing it back to us.  Because many
copies of the software are sold to end users through agents and
distributors, Wellspring Solutions will not have you in its
records until you do register.  Once registered, we can  keep
you informed of the following:

Latest product development news

Availability of new product releases

Other announcements

Customer Support

If you purchased your product directly from Wellspring
Solutions, Inc., and you need technical assistance, contact
Wellspring Solutions using one of the following methods:

Telephone:		1-508-865-7271 between 9am-5pm EST

BBS/Fax:		1-508 865-1113 anytime

Email:			support@wellspring.com

Write:			Wellspring Solutions, Inc.

					Technical Support, P.O. Box 150, Sutton, MA 						01590 USA

If you purchased your Wellspring Solutions product from a
distributor or reseller, please contact the distributor or
reseller who sold you your  product.

Bug Reports

Wellspring Solutions welcomes comments and reports on bugs that
VeriWell users may encounter.  In order to fix the problem, the
technical staff needs to reproduce it, therefore, if you are
reporting a bug, please send the whole module or code fragment
of the model via Email to: support@wellspring.com, or by
BBS/Fax, 1-508-865-1113.

Ordering Wellspring Solutions' Products

Wellspring Solutions' products can be ordered directly in the
U.S. by calling our toll-free number.

1-800-VERIWELL (1-800-837-4935), 9am-5pm EST

Additionally, Wellspring has several distributor sites located
outside the U.S.  In Europe, contact Acapella, Ltd.,
+44-703-769-008.  In Japan, contact Advanced Control Technology
(A.C.T.) at +81-426-44-5308.  All other regions outside the
U.S., call +1-508-865-7271.

If you have downloaded VeriWell from FTP or BBS, it is very easy
to convert the software to the full, unlimited registered
version by simply calling one of the phone numbers provided.

Info-VeriWell Mailing List

The Info-VeriWell mailing list is a reflector where a message
sent to the list is forwarded automatically to all subscribers. 
It is used as an efficient communications medium to inform
VeriWell users of new releases, news, hints, etc.  The
Info-VeriWell mailing list also allows VeriWell users to
communicate topics of interest to all users to other VeriWell
users, such as new-user questions, bug reports, work-arounds,
and hints.

We strongly encourage all users -- free and registered -- with
Email access, to subscribe to this list.

Send Email to:

Info-VeriWell-request@DMC.com

Use the word 'subscribe' in the body of the message and
information about the mailing list will be sent to you.

Receiving Updates

Wellspring Solutions regularly improves current revisions of the
software.  These updates are free and can be obtained in a
relatively open manner -- by the Bulletin Board System, File
Transfer Protocol, Email, or regular mail.

Once you register by mailing back the Registration Card found
with the product package, we can keep you informed of the status
of BBS and FTP.  Readers of the Info-VeriWell mailing list will
also be informed about the availability of upgrades.

Users without Email access should call the BBS periodically to
check on the availability of updates.  If you can't access BBS,
FTP, or Email, please call 1-508-865-7271 to request the update
be sent on floppy disk by regular mail.Bulletin Board System (BBS)

Wellspring Solutions maintains an electronic Bulletin Board
System (BBS) that is available by modem 24 hours per day 7 days
per week.  The BBS is always the first to receive new products,
updates, and bug fixes.  If you do not have Email access, you
can send messages and upload code fragments to the BBS for
problem diagnosis.

The BBS is divided into two sections:

A File area for uploading and downloading files

A Message area for sending and receiving messages (mail)

Both sections are further divided into areas for particular
product and interest categories.  The BBS is menu driven, and
usage is self-explanatory.  Use the menu selections to go to one
of the File areas to download or upload files or to one of the
Message areas to send or receive messages.

To use the BBS, you must have:

A Modem

If you are planning to download software from BBS, we strongly
recommend that you use a 9600-baud modem or faster (v.32 or
v.32bis).  We currently support up to 14400 baud (v.32bis).

Communications Software

Your communications software should support the Zmodem transfer
protocol.  Most files are approximately 500kb in size and will
take a few minutes to download at 9600 baud with Zmodem.  The
BBS also supports Xmodem and Ymodem.

We suggest that you familiarize yourself with the uploading and
downloading procedures of your communications software.

To log onto the BBS:

Make sure that your modem is set to 8-N-1 (8 bits, no parity,
one stop bit).

Use the communication software to dial 1-508-865-1113 (yes, that
is also our fax number).

Identify yourself, first and last name, and create a password.

	Note:	Once you have logged on successfully, BBS will have a
record of your name and password just as you have entered them. 
Make a note of this information for future login attempts.



Read the bulletins, answer the questions, and follow the menus
and steps to get to the file of interest.

Note:	The quality of the telephone lines can affect your ability
to connect and transfer data at high speeds.  If you experience
problems connecting, try using a lower baud rate.





File Transfer Protocol (FTP)

Many files and updates are available over the Internet via the
File Transfer Protocol (FTP) utility.  Wellspring's FTP site
address is <ftp.iii.net>.  Follow these instructions to access
Wellspring Solutions' files on iii.net:

Dial up ftp.  

After you are connected, you'll see the word 'Host:'.  Type
'ftp.iii.net' and a carriage return.

You'll be asked for a 'Username:'.  Type 'anonymous'; carriage
return.

Then you'll be asked for a 'Password:'  Type your complete Email
address; carriage return.

At the 'ftp>' prompt, type 'cd pub/pub-site/wellspring';
carriage return.Note:	The commands "ls" and "dir" can be used to
display the contents of the 'wellspring' directory and each of
its sub-directories.





At the 'ftp>' prompt, type 'cd' to whatever directory is of
interest; carriage return.

Type 'bin' [for binary]; carriage return.

Type 'hash' [shows download progress]; carriage return.

Type 'get <file>' [whatever file is of interest]; carriage
return.

The file you have chosen will begin to download.  When the
process is finished, you'll see the 'ftp>' prompt once again.

Type 'quit' to exit the utility.

If you need help in using FTP or want more information, consult
your FTP reference or ask your system administrator.

Electronic Mail (Email)

Wellspring Solutions will send updates to customers by Email,
however, this method is used only on a need basis because it
presents a few complications.  First, software sent by Email
must be encoded into

ASCII because only ASCII files can be transmitted by Email over
the Internet.  Secondly, software is generally too large to be
transmitted as one message (i.e.., VeriWell), therefore, it must
be sent as several messages.

We use uuencode to convert software for DOS and UNIX into ASCII
format.  Uuencode is usually included in the distribution of
UNIX systems.  Free uuencode versions are available for MS-DOS. 
If needed, Wellspring will provide a version of uuencode written
in BASIC to convert VeriWell upgrades to ASCII format.  Please
call 1-508-865-7271 for more information.

Wellspring files and updates for the Macintosh are transferred
by Email differently than for UNIX or MS-DOS.  We use the
shareware utilities StuffIt! and BinHex to compress and
decompress the files.  StuffIt! compresses the software and
BinHex 4.0 converts it to ASCII.

Regular Mail

Updates can also be sent on distribution media by regular mail. 
If you're not able to access any of the electronic methods
described above, BBS, FTP, or Email, or these methods are not
convenient for you, call 1-508-865-7271 and arrangements can be
made to mail you updates.

Recommended Publications

For a complete reference to Verilog HDL language, we recommend
that you refer to the following publications.

The Verilog HDL Language Reference Manual (LRM) 1.0

Wellspring Solutions highly recommends that VeriWell users
obtain a copy of the LRM, version 1.0, and use it in conjunction
with The VerWell User's Guide 2.0.  The LRM is available from
the Open Verilog International (OVI) organization.  Contact
information follows this section.  Version 2.0 of the LRM is
also available from OVI although not widely accepted in the
industry.

The Verilog Hardware Description Language, Second Edition

Written by Donald E. Thomas of Carnegie Melon University and
Philip R. Moorby, the creator of the Verilog language, this
tutorial bundles a 1000-line version of VeriWell/Free for DOS
and is published by Kluwer Academic Publishers, Norwell MA;

ISBN 0-7923-9523-9.

Digital Design and Synthesis with Verilog HDL

This Verilog book is written by E. Sternheim, R. Singh, Y.
Trivedi, R. Madhavan, and W. Stapleton, and is published by
Automata Publishing Co., San Jose, CA;

ISBN 0-9627488-2-X.

Open Verilog International (OVI)

The Open Verilog International (OVI) organization coordinates
the activities of Verilog HDL vendors and sponsors an annual
IVC, the International Verilog Conference.  Requests to be
placed on the OVI Newsletter Mailing List or inquiries related
to The Verilog HDL Language Reference Manual (LRM) can be
directed to:

Open Verilog International (OVI)

15466 Los Gatos Boulevard

Suite 109-071

Los Gatos, CA 95032

Tel: (408) 353-8899

Fax: (408) 353-8869

Email: OVI@netcom.com.

Wellspring highly recommends VeriWell users obtain a copy of the
LRM, version 1.0, and use it in conjunction with this VeriWell
User's Guide, 2.0.Chapter 2:	The VeriWell User's Guide

Chapter Two describes the scope, intent, organization, and
content of this VeriWell User's Guide 2.0.

How to Use This Manual

The VeriWell User's Guide 2.0 is divided into four Parts.  We
recommend that you read this section first, Part I, then turn to
Part IV, Your VeriWell Environment, for installation
instructions and to gain an understanding of how VeriWell works
with your particular operating and system set up.  Parts II and
III describe the VeriWell simulator and the VeriWell Preference
Modules.

Intended Audience

This guide assumes that the reader already has a working
knowledge of the Verilog HDL.  It is not intended as a Verilog
reference manual or a Verilog tutorial.  If you are not familiar
with Verilog, then you should obtain a copy of the Language
Reference Manual 1.0 from OVI.  The LRM is a complete reference
to Verilog HDL.  We also encourage you to obtain one of the
books described in the previous chapter (Recommended
Publications).

Scope of Manual

The purpose of this document is to describe the similarities and
differences between the features of VeriWell, version 2.0, and
Verilog HDL as defined in the Verilog Language Reference Manual
(LRM), version 1.0.  This guide also explains how to use the
VeriWell simulator and its Preferences within the currently
supported environments.

Since this user's guide makes numerous references to the LRM,
the definitive reference on which VeriWell is based, Wellspring
Solutions recommends that all VeriWell users have a copy of the
LRM, version 1.0.

Additional Verilog HDL related documents are listed in the
previous chapter.  New users are encouraged to read one or more
of the recommended books about Verilog.

Experienced XL users are advised to read the sections in this
document detailing the differences between VeriWell and
Verilog-XL.  XL users can use the manuals from Cadence Design
Systems, although there may be differences found in Cadence's
manuals that are not documented in the VeriWell manual.

Manual Organization

The VeriWell User's Guide contains a table of contents, Part I:
Introduction, Part II: VeriWell, Part III: VeriWell Preference
Modules, and, Part IV: Your VeriWell Environment.  The complete
Wellspring Solutions, Inc. Software License Agreement is found
at the end of the manual.

Part I:  Introduction

Chapter 1, Getting Acquainted, includes useful and important
information for VeriWell users.

Chapter 2, The VeriWell User's Guide 2.0, describes the scope,
intent, organization, and content of this manual.

Chapter 3, About VeriWell, presents a brief history of Verilog
HDL and the VeriWell product family.  It lists the major
differences between VeriWell and Verilog-XL and details
enhancements to VeriWell since version 1.2.

Part II:  VeriWell

Chapter 1, Using VeriWell, provides general instructions on how
to use and run VeriWell within any of the supported environments.

Chapter 2, VeriWell Feature List, presents a summary of all the
language constructs supported by VeriWell 2.0.

Chapter 3, OVI LRM Cross Reference, describes how VeriWell
deviates from the LRM by listing each section of the LRM and
describing all applicable deviations.

Chapter 4, VeriWell Implementation Notes, describes certain
implementation elements of VeriWell that are not covered or
would not be applicable in the LRM as well as unique VeriWell
implementations not documented elsewhere in this manual. 

Chapter 5, Implementation Differences from Verilog-XL, describes
the differences between the way VeriWell works and the way
Verilog-XL works.

Part III:  VeriWell Preference Modules

Chapter 1, Introduction, explains Wellspring's Modular
Architecture product offering.

Chapter 2, Gate-level and Timing Preference Module, describes
the added support to the VeriWell simulator for User-Defined
Primitives and Specify Blocks.

Chapter 3, WellspringWaves Preference Module, describes
Wellspring's full-featured waveform viewer available for
VeriWell for DOS and Windows.

Part IV:  Your VeriWell Environment

This section describes operating or system environment
characteristics of the currently supported ports.  Those aspects
of the VeriWell simulator that are dependent on a platform or an
environment are described in this section.  Such aspects include
system requirements, installation procedures (also described in
an on-line text document on the distribution media) and other
environment/platform-specific particulars.

Since all of the language aspects of VeriWell are common to all
ports, those aspects are covered in Part II, VeriWell, and this
section is written to be platform/environment independent.

Chapter 1, VeriWell for DOS, describes prerequisites and
procedures necessary to use VeriWell on IBM-compatible systems.

Chapter 2, VeriWell for Sparc, explains system prerequisites and
procedures necessary to use VeriWell on Sparc and
Sparc-compatible systems.

Chapter 3, VeriWell for Macintosh and Windows, describes the
prerequisites and procedures necessary to run VeriWell on a
68020-based Macintosh, or greater, and IBM-compatible systems
with Windows or Windows NT.

VeriWell Release Notes 

VeriWell Release Notes provide information on enhancements or
changes to version 2.0 since the VeriWell User's Guide 2.0 was
printed.  These Release Notes are documented separately and may
be included with the VeriWell product package.  If your VeriWell
product package does not contain a separate set of VeriWell
Release Notes, then there have been no significant enhancements
to be documented since your package was shipped.

If Wellspring prepares Release Notes after you receive your
package, we will automatically mail them to you so you can stay
up to date.  Additionally, we will include these same Release
Notes on FTP and BBS with the latest VeriWell version.

VeriWell Release Notes are intended to be either added to the
User's Guide or replace specific pages or sections of the guide.
 Instructions on how to merge release note documentation into
the User's Guide will accompany the set.Chapter 3:	About VeriWell

Overview of Verilog HDL

Verilog HDL, a hardware description language used to design and
document electronic systems, is the EDA industry's first
standard HDL.  It allows designers to describe their designs at
higher levels of abstraction, such as architectural or
behavioral, and provide a path to logic synthesis.  Verilog HDL
also allows for mixed-level designs, where users can describe
their design at both high and low levels of logic simulation and
synthesis.

Verilog HDL is the most widely used HDL with a user community of
more than 35,000 active designers who are choosing top-down
design and mixed-level design to contend with ever-increasing
design complexities and shrinking time to market cycles.

Verilog HDL was designed by Philip Moorby and introduced in 1985
by Gateway Design Automation.  Moorby built a simulator around
Verilog-XL in 1984-85, and continued to make a second major
contribution at Gateway with the algorithm for every fast
gate-level simulation.

Gateway Design Automation grew rapidly with the success of
Verilog-XL when it was acquired in 1989 by Cadence Design
Systems, Inc.

A proprietary language until 1990, Cadence brought Verilog HDL
to the public domain in May of 1991 with the formation of Open
Verilog International (OVI), the organization that oversees
Verilog-related activities .  Putting Verilog in the public
domain opened the market for other Verilog HDL-related software
companies to develop and expand resulting in broader acceptance
of the language.

Within just a few years, the market for Verilog-related tools
has grown substantially.  In 1994, it was well over $75M, making
Verilog HDL the most commercially significant hardware
description language on the market.

Verilog is now in the process of being standardized by the IEEE.
 The Design Automation Sub-Committee was formed in 1993 to
provide the IEEE Verilog standard 1364.  Under this
Sub-Committee is an active IEEE operating group that expects to
produce a Verilog standard draft ready for balloting in 1995. 
Wellspring Solutions has been an active participant in this
process.

About VeriWell

VeriWell is a comprehensive, OVI-compliant implementation of
Verilog HDL.  Through its development of VeriWell, Wellspring
Solutions has met Verilog users' needs for robust and affordable
Verilog-HDL design tools.

VeriWell supports a number of platforms and operating
environments.  These currently include:

MS-DOS for IBM-compatible PCs

Sparc and Sparc compatible systems running SunOS and Solaris

Macintosh

Windows, Windows NT

Linux

VeriWell is designed to be as portable as possible.  Nearly 100%
of the sources are shared between the different platform
versions.  The DOS version uses a DOS extender to compensate for
the shortcomings of DOS and to fully utilize the 32-bit
architecture of the 386/486/Pentium processors.

VeriWell supports the Verilog language as specified by the OVI
Language Reference Manual.  VeriWell was first introduced in
December, 1992, and is the first independently-developed
simulator to be written, from the first line of code, to be
compatible with the OVI standard and with Verilog-XL.  Because
it was developed on the PC, it was specifically designed to be
memory-efficient with relatively high performance.

VeriWell is used by ASIC designers and consultants for all pre-
and post-synthesis model development.  At the behavioral and RTL
levels, VeriWell is used to develop entire synthesizable models
and test environments.  At the structural level, VeriWell is
used to verify netlists generated by either synthesis tools or
schematic entry tools.

As a component of a large-scale top-down design methodology,
VeriWell is used in conjunction with other high-end
OVI-compliant simulators, such as Verilog-XL or Chronologic's
VCS, to develop behavioral, RTL and synthesis models in Verilog
HDL.  This complementary marriage between VeriWell and other
simulators enhances the design process and greatly reduces the
user's overall tool costs.  Verilog-XL users will recognize the
familiar user interface (single-step, trace, interactive
commands) and the fact that VeriWell supports command files,
input files, and log and key files.

In addition, the superior error-detection capabilities of
VeriWell finds most syntax and semantic errors on the first
pass.  This helps end the frustration of users who hitherto
would fix all reported errors only to find a new set of errors
reported.

Wellspring Solutions is committed to providing comprehensive,
compatible, and affordable design tools for Verilog users.  To
that end, Wellspring Solutions will continue to upgrade and
enhance the basic VeriWell simulator package and optional
Preference Modules to offer its customers quality products and
timely technical support.

What's New in VeriWell, Version 2.0

Since the release of VeriWell 1.2, Wellspring has added the
following functionality, platforms, and environments:

Gate-level and Timing support for all VeriWell environments

User-Defined Primitives (UDPs)

Specify Blocks

Timescales

Value Change Dump (VCDs)

Data Types

REAL

Operands

hierarchical names

Statements

assign/deassign, force/release

System Tasks and Functions

%s, %t, %e, %f, %g

$fopen/$fclose

$readmemh

$readmemb

$wwaves

$random

$test$plusargs

$dumpvars

$dumpfile

$dumpon/$dumpoff

$dumpflush

$dumpall

$bitstoreal

$realtobits

$itor

$rtoi

$realtime

$timeformat

$printtimescale



Command Line Options

-y (library directory)

Compiler Directives

`timescale

Predefined Plus Options

+libext+<ext>+<ext>...

+incdir+<directory1>+<directory2>+...

Macintosh

Linux

Windows, Windows NTPart II:		VeriWell

Chapter 1:	Using VeriWell

Chapter 2:	VeriWell Feature List

Chapter 3:	OVI LRM Cross-Reference

Chapter 4:	VeriWell Implementation Notes

Chapter 5:	Implementation Differences from Verilog-XLChapter 1:	Using VeriWell

Introduction

This chapter describes some basic techniques for getting started
with VeriWell.  Unless otherwise stated, the information in this
chapter is general for all operating and system environments
supported by VeriWell.  For platform-specific information, refer
to Part IV, Your VeriWell Environment.

VeriWell is an interpreted simulator.  This means that when
VeriWell starts, it reads in the source models, compiles them
into internal data structures, and then executes them from these
structures.  The structures contain enough information that the
source can be reproduced from the structures (minus formatting
and comments).

Once the model is running, the simulation can be interrupted at
any time by pressing control-C (or the "stop" button if using a
graphical user interface).  This puts the simulator in an
interactive command mode.  From here, VeriWell commands and
Verilog statements can be entered to debug, modify, or control
the course of the simulation.

Invoking VeriWell

VeriWell is invoked with one or more source files and zero or
more options.  An example of a minimal command line is:

veriwell model.v

This invokes VeriWell, and immediately starts executing the
source file "model.v".Note:	By convention, Verilog source files
use a ".v" suffix.



If there is no user intervention, the model will run to
completion. 

If there is more than one file, then each needs to be specified
on the command line:

veriwell cpu.v memory.v io.v

The order that the files appear in the command line is the order
that the files will be compiled.  In most cases the order is
irrelevant, but there are some cases where the order is
significant, particularly when using the same macros ("`define")
across files.

Frequently, it is desirable to cause VeriWell to enter
interactive mode before execution begins.  This is accomplished
by inserting the "-s" (stop) option:

veriwell -s cpu.v memory.v io.v

Another frequent command line option is "-t" which enables trace
mode at the beginning of the simulation:

veriwell -t cpu.v memory.v io.v

Command line options may appear in any order and anywhere on the
command line.  The following examples are identical:

veriwell -t -s cpu.v memory.v io.v

veriwell cpu.v memory.v io.v -s -t

veriwell cpu.v -t memory.v -s io.v

veriwell cpu.v memory.v -s io.v -t

Options are processed in the order that they appear on the
command line.  Files are processed in the order that they appear
after the options are processed.

Once invoked, the simulation can be controlled with simple
commands.  Also, VeriWell accepts any Verilog statement (but new
modules or declarations cannot be added).

Command Files

Often, there are many files and command line options that make
command lines unwieldy.  As an alternative to specifying
commands and options on the command line, they instead can be
contained in a file.  This so-called command file contains
source files and command line options separated by a new line.

Command files are read by VeriWell using the "-f" option.  For
example:

veriwell -f command.vc

This gets all source file names and options from the file called
"command.vc".Note:	By convention, command file names end with
the ".vc" suffix.





The command file would contain something like this:

cpu.v

memory.v

io.v

-s

-t

Command files can be combined with command line arguments. 
Command files can also be nested; that is, a command file can
contain a reference to another command file.  Source files and
options are processed as they are encountered.

Command Interaction

VeriWell allows commands and statements to be entered
interactively.  This can be used to control, observe, and debug
the simulation.

There are three ways to enter into simulation mode:

when control-C is pressed  (or the "stop" button is selected in
a GUI) while the simulation is running,

when the $stop system task is executed, or,

when the "-s" command line option is used.

When interactive mode is entered, the prompt will look like this:

C1>

Where "C" refers to the fact that VeriWell is in command mode,
and "1" refers to a sequential number of the completed command.

There are a number of interactive commands that can be entered
at the command prompt.  One is "." (period).  This resumes
execution of the simulation.  Another is "," (comma).  This
executes one Verilog statement and displays the next statement
to be executed.

Also, many Verilog commands can be typed in at the command line.
 For instance, $display can be typed to view the current value
of any variable; $scope can be typed to traverse the hierarchy;
$finish can be typed to exit the simulator.

When typing a Verilog command, remember that since all Verilog
commands require a terminating semicolon, that semicolon must
also be typed at the command line:

C1> $finish;More on Interactive Commands

Typing commands interactively can be used for controlling,
debugging, and monitoring the simulation.  There are probably
unlimited ways to use commands interactively, but here are some
useful examples:

1)  Terminating a simulation:

A simulation can be ended by typing "$finish;" at the command
line.Note:	A simulation can be terminated in a number of other
ways: Pressing control-C, pulling the file|quit menu item in a
GUI version, and, of course, allowing the simulation to run to
completion.





2)  Enabling and disabling trace:

Trace mode can be enabled and disabled by using the following
commands:  "$settrace;" and "$cleartrace;".

3)  Displaying variables:

Any variable can be displayed to view its current contents. 
Simply typing "$display(...);" will show the current value. 
Make sure that the scope is correct.  A common mistake is to
view a trace, pause the simulation, and type $display without
realizing that the variable may not be in the current scope.  In
interactive mode, the current scope is set using the $scope
system task.  It does not follow the scope of the simulation. 
For example:

C2> $scope (top.cpu1.iunit);

C3> $display (ireg);

The same can be expressed:

C2> $display (top.cpu1.iunit.ireg);

4)  Changing things:

Variables can be modified by using simple assignment statements:

C2> foo = 4 * bar;

5)  Timed simulations:

A simulation can be set to run for a certain length of
simulation time:

C2> #1000 $stop;.

This sets up a delay of 1000 simulation units.  When that has
passed, the $stop statement will be executed, pausing the
simulation.  The "." (period) continues the simulation after the
statement has been entered.

6)  Variable Watches (breakpoints):

Interactive statements can be used to stop the simulation when a
particular variable, or combination of variables, changes:

C2> @(top.cpu1.iunit.ireg) $stop;.

This will continue the simulation until the variable changes. 
However, the statement will not execute immediately after the
variable changes.  Rather, it will be executed sometime later in
the same time unit.

Input files

Commands can be put into a file automatically submitted to
VeriWell just before the simulation begins.  This is
accomplished with the "-i" command line option.  Any command
that is legal in interactive mode can also be sent via an input
file.

For example, assume the file "foo.vi" contains the following:

$settrace;

#1000 $stop;

This file is submitted with the following command:

veriwell -i foo.vi cpu.v ...

Debugging Techniques

Debugging Verilog code is more of an art than a science, but
here are some basic techniques:

trace and single step

One of the best ways to debug a model is to watch it execute. 
In VeriWell there is a trace mode that displays each statement
as it is executed.  To enable trace mode, type "$settrace;" at
the command line (it may also be executed from inside a model). 
When the simulation is resumed, each executed statement will be
displayed.  To disable trace mode, type "$cleartrace;".

It is often desirable to execute one statement at a time and
observe the effects of that statement.  Pressing the "," (comma)
at the command prompt executes a single Verilog statement and
displays it.

Since everything that is displayed is also sent to the log file
(veriwell.log by default), results of tracing can be viewed
after the simulation is complete.

showvars/variable trace

All the variables in a given scope can be displayed using the
$showvars system task.  $showvars also displays the information
about when the variable was last modified, specifically, the
simulation time, the file name, and line number of the reference.

variable breakpoints

VeriWell can be told to halt the simulations and enter into
interactive mode when a particular variable, or combination of
variables, changes.  The following example can be used either
from within the model or interactively:

@(variable) stop;

test modules

One technique for testing models it to write a test module that
communicated with the model under test.  VeriWell allows more
than one top-level module.  One top-level module would serve as
the top-level for the model under test.  A second top-level
module can be used as a test bed or monitor module that
references signals in the other module using hierarchical names.
 This is a non-intrusive technique that requires no changes to
the original model.

Interactive Commands

Continue ('.') [period]

Resume execution from the current location.

Single-step with trace (',') [comma]

Execute a single statement and display the trace for that
statement.

Single-step without trace (';') [semicolon]

Execute a single statement without trace.

Current location (':') [colon]

Display the current location.

Typically, the kinds of Verilog statements executed
interactively are used for debugging and information-gathering. 
$display and $showvars can be typed at the interactive prompt to
show the values of variables.  $scope and $showscopes can be
typed to traverse the model hierarchy.  $settrace and
$cleartrace will enter and exit trace mode. Typing "#100;
$stop;" will stop the execution after 100 simulation units.

Command Line Options

-c (compile only)

Causes the model to be compiled only and not simulated.

-f <commandfilename> (command file)

Reads additional command line options from a file, including
source file names.  Each option or source file name is separated
by a new line.  Comments are allowed in command files.  Command
files may be nested.  This option is generally used to specify
the names of the source files so that they do not have to be
typed in every time the simulation needs to be rerun.  Also, if
passwords are applicable (on workstation versions), all
passwords can be put into a single command file.  For example:

veriwell -f command.vc

In command.vc: 

	cpu.v		memory.v		bus.v		top.v		-s

-i <inputfilename> (input file)

Specifies a file that contains interactive commands to be
executed as soon as interactive command mode is entered.  This
option should be used with the "-s" option.  This can be used to
initialize variables and set time limits on the simulation.

-s (stop)

Causes interactive mode to be entered before the simulation
begins.

-t (trace)

Causes all statements to be traced.  Trace mode may be disabled
with the $cleartrace system task.

-l <logfilename> | "nolog" (log name)

Changes the default name of the log file, to which all output is
copied.  Specifying "nolog" disables the log file.  By default,
the log file is called "veriwell.log".  The log file can be
changed, enabled, and disabled at run time using the $log and
$nolog system tasks.

-k <keyfilename> | "nokey" (key name)

Changes the default name of the key file, which retains a log of
all keystrokes entered during the simulation run.  Specifying
"nokey" disables the key file.  By default, the key file is
called "VeriWell.key".  The key file can be changed, enabled,
and disabled at run time using the $key and $nokey system tasks.

-y <directory> [library directory]

Specifies the path of a directory where Veriwell will search for
modules not defined in the file list.  This is used to implement
libraries.  If this option is specified, then any undefined
modules found during the compiling of the model will be searched
in the given directory.  The name of the file must be the same
as the name of the module.  The suffix is determined by the
"+libext" option.

-p<passwd>

This option is for versions of VeriWell for Sparc that require a
password on the command line (or in a command file).  The
password is an 8-digit hex number supplied with the distribution.

Note:	There are no spaces between the -p and the number <passwd>.



Predefined Plus Options

+maxdelays/+mindelays/+typdelays

Specifies which delay should be used in the "min:typ:max"
expressions.

+define+<macro name>+<macro name>...

Defines macro names from the command line, generally for use
with conditional compilation directives.  Any number of macros
can be defined.

+synopsys

Displays warnings at compile time for constructs that are either
not supported or ignored by Synopsys HDL Compiler.

+noshow_var_change

By default, VeriWell keeps track of the location and simulation
time of where variables are last written.  This is displayed in
$showvars.  This feature may cause a slight performance
degradation, so it can be disabled with this option.

+libext+<ext>+<ext>...

Specifies the filename extension used when searching for
libraries in the library directory.  This is most often used
with the "-y" option.  For example:

veriwell cpu.v -y /design/libs +libext+.vl+.vv

This will search the directory /design/libs for libraries whose
filename ends with ".vl" and ".vv".

Note:	On DOS- and Windows-based systems, the slashes are
reversed.



+incdir+<directory1>+<directory2>+...

Specifies the directories that VeriWell searches for include
files. 

Note:	All characters between the pluses are used in the
directory name.



Compilation

During the compilation stage of VeriWell, the three phases of
the process are displayed to show the progress of the
compilation.  These three phases are:

Phase 1:	The files are read and converted into an internal data
structure.  Syntax errors and semantic errors regarding
undeclared variables or illegal use of variables (i.e. the most
common types if errors) are reported in this phase.

Phase 2:	The model hierarchy is built, module ports are
connected, and storage for variables is allocated in this phase.
 If any module is instantiated more than once, its structure is
copied as many times as needed in this phase.  Also, module
parameters are propagated.  Errors reported in this phase deal
with missing modules, irregularities of the parameters, and
out-of-memory errors during the allocation.

Phase 3:	The entire structure is reparsed during which time
forward references to tasks and functions are resolved,
hierarchical names are resolved, and expression sizes are
determined.  Errors detected in this phase include semantic
errors dealing with hierarchical references that could not be
detected in phase 1, illegal references to functions and tasks,
port size discrepancies, and illegal expression sizes.

Note:	Most memory is allocated in the first two phases of the
compilation.



Chapter 2:	VeriWell Feature List

The following represents the definitive list of language
constructs supported by VeriWell 2.0.

Data Types

Static types:

REG

REG arrays		

INTEGER

INTEGER arrays	

TIME

REAL

MEMORIES

PARAMETER

Nets:

WIRE/TRI

WOR/TRIOR

WIAND/TRIAND

TRI0

TRI1









Operands (Conforms to Expression Bit-Length Rules)

number

net

register

integer, time

net bit-select

register bit-select

register part-select

net part-select

memory element

function

system function

strings

min:typ:max

hierarchical names

Operators

concatenation

arithmetic  +, -, *, /

modulus

relational > < >= <=

logical negation

logical and

logical or

logical equality

logical inequality

case equality

case inequality

bit-wise negation

bit-wise and

bit-wise inclusive or

bit-wise exclusive or

bit-wise equivalence

reduction and

reduction nand

reduction or

reduction nor

reduction xor

reduction xnor

left shift

right shift

conditional (?:)



Built-in Primitives

and

nand

nor

or

xor

xnor

buf

not

bufif0

bufif1

notif0

notif1

tran

tranif0

tranif1



User-Defined Primitives

combinational

sequential

Statements

Continuous assignments

Net assignments

Procedural assignments

Blocking procedural

Non-blocking procedural assignments (<=)

forever

#delay

repeat

while

for

Intra-assignment delay

defparam

if-else

case

casex

casez

@

@(posedge)

@(negedge)

begin/end

fork/join

named blocks

always

initial

tasks

functions

disable

assign/deassign

force/release







Hierarchical Structures

Port connections by ordered list

Port collapsing

Named Ports

Hierarchical references

Specify Blocks

$setup

$hold

$period

$width

$skew

$recovery

$setuphold

$nochange

specparam



System Tasks and Functions

$display[bho]/$write[bho],

%h, %o, %d, %b, %c, %m, %x, %t, %s, %f, %e, %g

$fdisplay[bho]/$fwrite[bho]

$strobe[bho]/$fstrobe[bho]

$monitor[bho]/$fmonitor[bho]

$monitoron/$monitoroff

$fopen/$fclose

$readmemh/$readmemb

$time/$stime

$stop, $finish [no arguments]

$settrace, $cleartrace

$scope, $showscopes

$log/$nolog

$showvars

$key/$nokey

$input

$showstats

$wwaves

$random

$test$plusargs

$dumpvars

$dumpfile

$dumpon/$dumpoff

$dumpflush

$dumpall

$bitstoreal

$realtobits

$itor

$rtoi

$realtime

$timeformat

$printtimescale



Command Line Options

-c (compile only)

-f (command argument)

-i (input file)

-s (stop)

-t (trace)

-l (log name).  The log file can be disabled with the command
line argument "-l nolog".

-k (key name).  The key file can be disabled with the command
line argument "-k nokey".

-y (library directory)

Compiler Directives

`define

`ifdef, `else, `endif

`include

`timescale

Predefined Plus Options

+maxdelays/+mindelays/+typdelays

+define+<macro name>+<macro name>...

+synopsys (displays warnings for constructs unsupported or
ignored by Synopsys HDL Compiler 2.x.)

+noshow_var_change (disables tracking of location and time of
each variable update)

+libext+<string> (library file extension)

+incdir+<directory>+... (include-file search rules)

Interactive Commands

Interactive statements (compile and execute a normal behavioral
statement)

. (continue with the simulation)

, (step and trace a single statement)

; (step a single statement)

: (colon)

Limitation Summary

Register and net vectors are limited to 262,080 bits

Bit-qualified decimal numbers are limited to 32 bits (i.e.
32'd1234).  Bit qualified numbers of other radii are limited to
262,080 bits.

All expressions representing controls are limited to 32 bits. 
These are: delays, repeat counts, shift counts, array indices,
and bit- and part-select indices.Note:	The indices for a vector
may be any number up to 4G (the highest number represented in 32
bits), but the range must not be larger than 262,080.

		Delay expressions are 32 bits wide.





Chapter 3:	OVI LRM Cross-Reference

This chapter is a cross-reference into the OVI Language
Reference Manual (LRM 1.0), in which all differences between the
LRM and the Verilog implementation of VeriWell are noted.

Items in 'bold' in this section are implemented in VeriWell.  If
no note appears after a section title, then VeriWell implements
that aspect of VeriWell verbatim.  If a note does appear, then
it either documents an implementation-dependent aspect or it
describes a restriction. 

A restriction is preceded by one asterisk (*) which indicates
that the restriction will be lifted in a planned enhancement of
VeriWell.



1	Introduction

2	Lexical Conventions

2.1		Operators

2.2		White Space and Comments

2.3		Numbers

* Sized decimal numbers (e.g. 5'd31) limited to 32 bits; Machine
size is 32 bits

2.4		Strings

2.5		Identifiers, Keywords, and System Names

Identifiers are limited to 128 characters

3	Data Types

3.1		Value Set

3.2		Registers and Nets

* 3.2.3 Declaration Syntax: Scalared, Vectored, charge strength,
and drive strength are not implemented

3.3		Vectors

3.3.1 Specifying Vectors: Maximum vector length is 262,080 bits

* 3.3.2 Vector Net Accessibility: Vectored and scalared key
words are not implemented

3.4		Strengths

* Not supported

3.5		Implicit Declarations

3.6		Net Initialization

3.7		Net Types

* 3.7.3 trireg Net: Not implemented

* 3.7.5 supply Nets: Not implemented

3.8		Memories

3.9		Integers and Times

3.10		Real Numbers

3.11		Parameters

Range specifications are allowed

4	Expressions

4.1		Operators

4.2		Operands

4.3		Minimum, Typical, Maximum Delay Expressions

4.4		Expression Bit Lengths

5	Assignments

5.1		Continuous Assignments

* Scalared, Vectored, Charge Strength, and drive strength are
not implemented

5.2		Procedural Assignments

5.3		Accelerated Continuous Assignments

6	Gate and Switch Level Modeling

6.1		Gate and Switch Declaration Syntax

* Strengths not implemented

6.2		and, nand, nor, or, xor, and xnor Gates

6.3		buf and not Gates

6.4		bufif1, bufif0, notif1, and notif0 Gates

6.5		MOS Switches

6.6		Bidirectional Pass Switches

6.7		cmos Gates

6.8		pullup and pulldown Sources

* Not implemented

6.9		Implicit Net Declarations

6.10		Logic Strength Modeling

* Not implemented

6.11		Strengths and Values of Combined Strengths

* Not implemented

6.12		Strength Reduction by Non-Resistive Devices

* Not implemented

6.13		Strength Reduction by Resistive Devices

* Not implemented

6.14		Strength of Net Types

* Not implemented

6.15		Gate and Net Delays

* 6.15.2 trireg Net Charge Delay: Not implemented

7	User-Defined Primitives (UDPs)

7.1		Memory Usage and Performance Considerations

7.2		Syntax

7.3		UDP Definition

7.4		Combinational UDPs

7.5		Level-Sensitive Sequential UDPs

7.6		Edge-Sensitive UDPs

7.7		Sequential UDP Initialization

7.8		UDP Instances

7.9		Compilation

7.10		Symbols to Enhance Readability

7.11		Mixing Level-Sensitive and Edge-Sensitive Descriptions

7.12		Reducing Pessimism

7.13		Level-Sensitive Dominance

7.14		Processing of Simultaneous Input Changes

7.15		Summary of Symbols

7.16		Examples

8	Behavioral Modeling

8.1		Behavioral Model Overview

8.2		Procedural Assignments

8.3		Conditional Statement

8.4		Case Statement

8.5		Looping Statements

8.6		Procedural Timing Controls

* 8.6.6 Intra-Assignment Timing Control: "repeat (x)@(...)" not
implemented

8.7		Block Statements

8.8		Structured Procedures

9	Tasks and Functions

9.1		Distinctions between Tasks and Functions

9.2		Tasks and Task Enabling

9.3		Functions and Function Calling

10	Disabling of Named Blocks and Tasks

11	Procedural Continuous Assignments

12	Hierarchical Structures

12.1		Modules

12.2		Overriding Module Parameter Values

12.3		Macro Modules

* Macro Modules are not implemented

12.4		Ports

12.4.6 Port Collapsing: See Implementation Notes

12.4.7 Port Connection Rules: See Implementation Notes

12.5		Hierarchical Names

12.5.3 Upward Name Referencing: See Implementation Notes

12.6		Scope Rules

13	Specify Blocks

13.1		Declaring Parameters in Specify Blocks

13.2		Module Path Delays

* 13.2.1 Describing Module Paths: Only full paths are supported;
using parallel paths will generate a warning

* 13.2.13 Global Path Pulse Control: Not supported

* 13.2.14 Pulse Control for Specific Modules and Module Paths:
Not supported

13.3		Timing Checks

13.4		Using Path Delays and Timing Checks in Behavioral
				Descriptions

13.5		Interactive Back Annotation

A	Formal Syntax Definition

Subset as outlined above

B	System Tasks and Functions

B.1		The Display and Write Tasks

B.1.2 Format Specifications: %h, %o, %d, %b, %c, %m, %x, %t, %s,
%f, %e, %g are implemented

* B.1.5 Strength Format: Not applicable since strengths are not
implemented

B.2		Strobed Monitoring

B.3		Continuous Monitoring

B.4		Timescale Systems Functions

B.5		Timescale System Tasks

B.6		Simulation Time--The $time Function

B.7		Finish System Task

B.8		Functions and Tasks for Reals

B.9		Timing Checks

C	Compiler Directives

C.1		'define

C.2		'default_nettype

* Default net type is always Wire

C.3		'unconnected_drive and 'nounconnected_drive

* Not implemented

C.4		'resetall

* Not implemented

C.5		'timescale

D	List of System Task and System Function Keywords

D.1		$bitstoreal

D.2		$countdrivers

* Not implemented

D.3		$display

D.4		Value Change Dump File Tasks

D.5		File Output

D.6		Finish

D.7		$getpattern

* Not implemented

D.8		$history

* Not implemented

D.9		$incsave

* Not implemented

D.10	$input

D.11	$itor

D.12	$key and $nokey

D.13	$list

* Not implemented

D.14	$log and $nolog

D.15	$monitor, $monitoron, $monitoroff

D.16	$printtimescale

D.17	$readmemb and $readmemh

D.18	$realtime

D.19	$realtobits

D.20	$reset, $reset_count, $reset_value

* Not implemented

D.21	$restart

* Not implemented

D.22	$rtoi

D.23	$Saving and Restarting

* Not implemented

D.24	$scale

D.25	$scope

D.26	$showscopes

D.27	$showvars

Takes zero or one argument; does not display driver information

D.28	$readmemb and $readmemb

D.29	$stime

D.30	$stop

D.31	$strobe

D.32	$time, $stime, $realtime

D.33	$timeformat

D.34	$write

E	List of Compiler Directive Keywords

E.5		'define

E.7		'ifdef, 'else, 'endif

E.8		'include

E.9		`timescaleChapter 4:	VeriWell Implementation Notes

Except for the following implementations, VeriWell behaves
exactly as specified by the OVI LRM and Verilog-XL.

Port Collapsing

In some implementations of Verilog,  if two nets are connected
together via a port, the port is "collapsed", that is, combined
into one net.  In VeriWell, module ports are connected using
transparent continuous assignments.   If a register is connected
to a net, then the port propagation does not occur immediately
when the port changes; rather it is scheduled for later in the
same simulation time.  But, when a net is connected to a net,
then a collapsed port is emulated by forcing the propagation to
occur instantly.  The effect of this implementation is
transparent to the functionality of the model being simulated,
but becomes visible during trace.

Port Connections of Different Net Types

VeriWell does not check for the legality of connecting different
net types through the hierarchy.  For example, if a parent
module instantiates a child module, and the net on the parent's
side of a port is a "tri1" while the net on the child's is a
"tri0", an oscillation will result.

To use tri1, tri0, triand, and trior as ports effectively in
VeriWell, they should be declared only in the top-most level in
the hierarchy.  All lower-level connections should be declared
as wire or tri.

Pullup/Pulldown Workaround 

When modeling an open-collector bus, a common technique is to
have a "pullup" or "pulldown" gate drive a "wire" net and have
drivers pull the bus in the opposite direction with a greater
strength when asserting a signal.  In VeriWell, drive strengths
are not implemented, therefore, this technique will generate an
unknown (X) value when a driver attempts to drive a signal in
the opposite direction as the pull.

The preferred method for modeling open-collector buses is to use
the "triand" or "trior" nets for pullup and pulldown buses,
respectively.  This net type should only appear in the highest
level of the hierarchy in which the bus exists.

Using Trace

Trace is an indispensable tool for debugging Verilog programs. 
It displays each statement as it is being executed.  Depending
on the statement, the statement's results are also displayed.

There are three ways to enable trace.  One is to specify the
"-t" option at the command line.  Another is to execute the
system task $settrace from either the program or from the
interactive command line.  Also, a single statement will be
executed and traced by entering a comma at the interactive
command line.  (Multiple commas may also be entered which
executes the respective number of statements.)

If a model uses continuous assignments or ports, VeriWell
displays the activation of these as part of the trace as soon as
the activation occurs.  For example, given the continuous
assignment "assign foo = bar;", when bar changes, the continuous
assignment is executed immediately, and this is displayed in the
trace.1

Since port connections are implemented as continuous
assignments, it may take several steps for a signal to propagate
from an output port to an input port, especially in cases where
there are several ports connected to a net.  Trace shows part of
this propagation.  Signals emanating from an output port travel
upward to its parent module; it then travels back down to other
connected ports.  Each time a signal reaches a new port, the net
connected to that port is evaluated and the results are
displayed in the trace.

Predefined Macro "__VERIWELL__"

The macro "__VERIWELL__" is predefined so that statements such
as:

`ifdef __VERIWELL__

can be used for VeriWell-specific code, such as for waveform
display.

Simulation Statistics

The non-standard system task, $showstats, displays statistics
about the current simulation, including the amount of memory
used and the amount available.  Some of the information is
provided for diagnostic purposes only.

Displaying Location of Last Value Change

In VeriWell, the $showvars system task optionally displays the
location in the module, as well as the simulation time, of the
last time variables were written.  This information is updated
even if the value did not change (i.e. the new data is the same
as the old data).

Tracking this update information may affect the performance of
the simulation slightly.  If this is a problem, this feature can
be disabled with the +noshow_var_change command line option.

User Interrupt

Pressing Control-C or Control-Break (in DOS) during simulation
will put VeriWell into interactive mode.  Pressing either during
compilation will halt the compilation and exit to the operating
system.Chapter 5:	Implementation Differences from Verilog-XL

Introduction

Chapter Five describes the differences between the way VeriWell
works and the way Verilog-XL works.  Note that these differences
are subtle and will not affect the execution of well-written
Verilog models.

Event Ordering

The order that events are scheduled and executed is consistent
with Verilog-XL to the extent possible.  The reason for doing
this is not so that models are guaranteed to work under both
VeriWell and Verilog-XL, rather, VeriWell was designed such that
users can trace models in VeriWell and in Verilog-XL with little
noticeable difference.  However, it should be noted that models
that depend on the order of execution are considered to be not
well-written since they reflect race conditions and may perform
unpredictably in other vendor's Verilog, or even in future
releases of VeriWell (or Verilog-XL).

In some cases, the order of net scheduling may be different. 
This is because Verilog-XL schedules nets differently depending
on the type of net, whether it is sourced by a continuing
assignment, and net assignment, or a port, and whether a port is
collapsed.   In most cases, net scheduling will track that of
Verilog-XL.

Module Ports and Port Collapsing

Port connections are implemented as continuous assignments in
VeriWell.  Rules for port connections are similar to those of
Verilog-XL.  There are some differences.  In Verilog-XL, under
certain circumstances, ports are "collapsed", that is, if each
side is a net, then one of the nets disappears and only one is
used.  This is a performance enhancement.

VeriWell emulates port collapsing by immediately propagating
values across ports that have been "collapsed".  This is unlike
Verilog-XL, which actually combines nets that have been
collapsed.  Verilog-XL will expand vector nets into arrays of
scalar nets if a port connects two different sized nets, or if
one or both sides are concatenations or part selects.  VeriWell
does not implement expansion of nets, so it could not handle
these cases with building continuous assignments.

VeriWell will "collapse" a port if both sides of a port are
scalar nets or if both sides are vector nets.  Therefore, there
are some cases when VeriWell will not collapse a port, but where
Verilog-XL will.  This may cause a disparity in the way nets are
scheduled in the two simulators.

Control Expressions Limited to 32 Bits

Expressions used by VeriWell for control are limited to 32 bits.
 This includes repeat counts, delay values, part- and bit-select
and array index expressions, and shift counts.  A compile-time
error will result if the expression attempts to evaluate a
number greater than 32 bits.

$Monitor

Unlike Verilog-XL, the $monitor statement will be triggered if
any variable in the argument list changes.  In Verilog-XL,
$monitor changes only when and argument expression changes.  For
example, the statement:

$monitor (a + b);

will not be triggered if both a and b changes, but the sum stays
the same.  In VeriWell, the statement will be triggered in this
case.

Scoping

VeriWell uses a different technique of storing variables than
Verilog-XL.  Variables in models are handled the same, but in
interactive mode, variables can be accessed in parent modules
without scoping, unless, of course, that variable has been
redefined in a lower scope.  For example, if a register 'a_reg'
is defined in a top-level module and $scope points to some lower
level module, typing $display (a_reg) will execute legally in
VeriWell, but not in Verilog-XL.

Key File

The key file in VeriWell will capture control-C, but this cannot
be fed back into VeriWell as input file because there is no
information on where in the simulation the control-C occurred.Part III:	VeriWell Preference Modules

Chapter 1:	Introduction

Chapter 2:	Gate-level and Timing Preference

Chapter 3:	WellspringWaves PreferenceChapter 1:	Introduction

Modular Architecture

With the release of VeriWell 2.0 in March 1995, Wellspring
introduced the concept of Modular Architecture, that is, the
offering of major aspects of the Verilog language separately
from the core simulator.  The core simulator, VeriWell, supports
the behavioral and register-transfer level aspects of the
language.  Other aspects are supported in the form of "User
Preferences".  These preferences are made available separately
from the core simulator so that only the required aspects of the
language need be obtained.

Not everyone uses the entire language, therefore, it fits with
our philosophy of  'providing low-cost, quality Verilog tools'
to unbundle certain major aspects of the Verilog language.  This
enables users to determine when to buy specific functionality
Preferences to suit their own needs.

In addition, some graphical front-ends and other features that
are separately available are also Preferences modules.

This part of the User's Guide describes each Preference
separately.









































Chapter 2:	Gate-level and Timing Preference

The Gate-level and Timing Preference adds to the core simulation
User-Defined Primitives (UDPs) and Specify Blocks.  For the most
part, these work exactly as described in the OVI LRM.  However,
there are some implementation details and peculiarities unique
to VeriWell.

User-Defined Primitives and Memory Usage

User-Defined Primitives (UDPs) are used to define combinatorial
primitives and two-state devices.  In VeriWell, the UDP is
implemented to be optimized for performance.  This is
accomplished by building a table in memory for each UDP
definition.  Only one such table is used for each UDP
definition; every instance of the definition uses the same table.

The table size is very large when the number of inputs exceed 6.
 For this reason, the maximum number of inputs is 10 (9 for
state UDPs).  The maximum table size is approximately 256kb.

Specify Blocks

Specify Blocks are used to define pin-to-pin timings and
setup-and-hold checks.  In VeriWell, Specify Blocks work just as
described in the LRM.  However, there are some differences.

In VeriWell, there is no concept of expanded nets.  Nets that
are defined as vectors are not split into individual nets and
cannot have their own timing information.  Therefore, certain
combinations of timing specifications will be ignored. 
Specifically, there are two ways to describe module paths.  One
is the so called parallel case ("=>") and the other is the full
case ("*>").  In VeriWell, both cases are treated as if they
were defined as the parallel case.  This does not pertain to
scalar nets..  

VeriWell supports all of the defined setup and hold systems
tasks.Chapter 3:	WellspringWaves Preference

Introduction

This chapter is included for users of WellspringWaves, a
Preference module that can be used concurrently with the
registered, PC-based versions of VeriWell.  WellspringWaves is a
Windows-based, full-featured optional waveform viewing utility. 
It features smooth scroll, zoom, radix change, dynamic grouping,
and full control of colors and fonts.  It runs under Windows 3.1
or later and under OS/2 2.1 or later.

WellspringWaves Syntax

WellspringWaves reads a compressed data file generated by a
VeriWell simulation session and displays its contents in the
form of familiar waveforms.  To generate the data file, the
simulation model must be slightly modified to enable capture of
the desired signals.  To do this, the $wwaves task is used.  The
syntax for $wwaves is similar to that of $gr_waves (used with
Cadence's waveform viewer).  In fact, you can use "$gr_waves" as
a synonym for $wwaves.

The syntax for $wwaves is:

$wwaves ("Signal Name", signal [, "Signal Name", signal [,...]]);

"signal" is the variable name of the signal to be captured. 
"Signal Name" is a string that is used in the WellspringWaves
display to identify the signal.  Note that the arguments are
always in pairs.  There is a limit of 256 pairs.  Signals can be
hierarchical references, concatenations, or legal expressions.

$wwaves must only be called once, generally from within an
INITIAL block.  Once enabled, it will capture its argument
signals each time one changes value.  Signal information is kept
in a data file called

"$vw$ave$.wav"

This file is always kept in the directory in which the
simulation is being run.

Arguments to $wwaves indicate which nets or registers are to be
displayed.  The grouping and ordering of signals can be done
within the WellspringWaves environment.  WellspringWaves also
allows the user to zoom in and out, scroll, and change radix,
colors, and fonts.

What is Included

WellspringWaves consists of several files and is shipped on a
single, separate floppy.  On the distribution disk, these files
are compressed and archived into a single "zip" file called
wwaves.zip.  A utility, unzip.exe,  is included on the
distribution disk for uncompressing wwaves.zip.

Several files will be extracted, including wwaves.exe, the
executable file, and wwaves.ini, the initialization file.

Besides other information, wwaves.ini contains the path of the
data file.  The default is to point to the included
WellspringWaves example data file.  If desired, this could be
changed before WellspringWaves is invoked for the first time, or
can be used to learn WellspringWaves.  wwaves.ini can be edited
using a DOS-based editor, using Windows' Notepad, or through the
WellspringWaves menus.

Installing WellspringWaves

To install WellspringWaves, simply create a directory, copy the
files from the distribution disk to the target directory, and
uncompress the files using the command:

unzip wwaves

Following are the procedures to install WellspringWaves.

Create a new directory and change to it

It can be called anything, such as "WWAVES".  It does not
necessarily have to be a top-level directory, but
WellspringWaves should have its own directory.

Insert the distribution in the floppy drive

Copy the contents into the new directory (e.g. "copy a:*.*").

Run the unarchive utility: "unzip  wwaves"

This should generate about 10 files, most with the ".DLL" suffix.

Invoke Windows

Select the menu item File|New

Press the "Program Group" radio button and "OK"

In the "Description" box, type "VeriWell"

A new group will appear.

Again, select "File|New"

Press the "Program Item" radio button and "OK"

Use "Browse" to select "wwaves.exe" from the new directory

Press "OK"

A balloon icon will appear.  WellspringWaves is now ready to use.

Using WellspringWaves for the First Time

The first time WellspringWaves is invoked, a sample data file
will appear.  Note:	If a dialog box appears with the message
"Error: BeginTime not understood", then WellspringWaves has not
been able to detect the presence of the hardware key.  Please
call Customer Support for assistance.





VeriWell with WellspringWaves

VeriWell communicates with WellspringWaves using an intermediate
file (typically called $vwa$ve$.wav).  VeriWell generates this
file when encountering the $wwaves system task.  VeriWell
continues to update this file during its simulation. 
WellspringWaves can be directed to read this file during or
after the simulation, and display the appropriate desired
waveforms.

WellspringWaves is a Windows 3.1 application (it will also run
under Windows NT and OS/2 in a seamless or WIN-OS/2 window).

Note:	VeriWell for DOS can be run in a DOS window under Windows
since it is DPMI-compliant.  Therefore, it is possible to run
VeriWell in Windows alongside of WellspringWaves.



Note:	WellspringWaves cannot display a waveform of a current
simulation.  VeriWell must complete the simulation and exit,
then WellspringWaves can be used to display the desired
waveforms.





Using WellspringWaves

WellspringWaves is very easy to use and for the most part
self-explanatory for the seasoned Windows user.  For for the
novice user, the functions are described below.

The Waves window is the main window.

Pressing the left mouse button within the waves places a
vertical line (point) at the nearest edge of the wave on which
the mouse is pointing.

Likewise, pressing the right button of the mouse places a second
vertical line (mark) at the nearest edge of the wave on which
the mouse is pointing.

The status bar at the top displays the simulation time of the
left margin, the right margin, the left point, the right point
and the difference between the point and the mark.

There are two scrollbars, one at the bottom and one at the left
of the signal names.  Both scrollbars are controlled in the same
way.  The left mouse button is used to drag the scollbar; the
right button shrinks and grows the scrollbar, which causes a
zoom in or zoom out.





Figure 1: The Waves WindowPart IV:	Your VeriWell  Environment

Chapter 1:	VeriWell for DOS

Chapter 2:	VeriWell for Sparc

Chapter 3:	VeriWell for Macintosh and Windows

Chapter 1:	VeriWell for DOS

Introduction

This chapter describes the prerequisites you must meet and the
procedures you must complete to install VeriWell successfully on
your PC.  This chapter also contains information about VeriWell
that applies only to the DOS environment, including using the
hardware key, running VeriWell with the DOS Extender, and other
DOS considerations relevant to memory display and interaction.

VeriWell for DOS uses a "DOS extender" to put the host processor
into "protected mode" which then utilizes the full capabilities
of the processor.  It supports up to 64MB of physical memory or
32MB for virtual memory.  A text file included with the
distribution contains detailed information on the configuration
and use of the DOS extender.  

VeriWell for DOS requires the use of a hardware key which is
shipped with the complete product package.  The hardware key is
plugged into a printer port of the system.  A printer can be
connected to the other side of the key.  The existence of the
key is transparent to all printer operations.

If VeriWell is invoked without the key, it will still run, but
with certain limitations.  These limitations are described in a
text file that is included with the distribution. 
TheVeriWell/Free version, readily available through FTP, BBS, or
by mail, is used without the hardware key as a teaching tool for
learning Verilog or for running small simulations.

Before You Begin

Make sure you have all of the following items before you begin
the installation procedure.

Hardware Key.  You must attach this device to the printer port
of your PC to enable the use of the VeriWell software.

Distribution diskette.  This diskette contains the compressed
files of the VeriWell software, a utility to uncompress them,
and various on-line text and documentation files.

A blank, formatted high-density diskette.  You need this
diskette to make a backup copy of your distribution diskette.

System Requirements

VeriWell for DOS requires:

IBM-compatible PC (386, 486, Pentium) using DOS 5 or later

2 MB of RAM, 2MB of disk space

Note:	Up to 32 MB of disk space is needed if virtual memory is
enabled in the DOS extender.



What is Included

The contents of the files included with VeriWell are described
in your distribution media.  VeriWell may be distributed in
several ways.  If you received the software electronically (BBS,
FTP, Email), then, most likely, all of the files are compressed
into a single "zip" file.  This requires that an "unzipper" be
used, such as PKUNZIP version 2.x, or UNZIP.  If you received
VeriWell on a floppy disk, then some files are zipped, but the
unzip utility is included.

VeriWell for DOS Installation Summary

A summary of the steps you must follow to install VeriWell on
your PC successfully appears below.  The section that follows
the summary, Installing VeriWell for DOS, describes the
procedures you must perform to complete each step.

Attach the hardware key to your PC's parallel printer port. 

Create a directory (mkdir) and change to (cd) a target directory
on your hard drive.  You can give this directory any name you
choose.

Copy the entire contents of the distribution diskette to the
target directory.

Make a backup copy of the distribution diskette files by copying
the contents of the target directory onto a blank diskette.

Use the UNZIP utility provided on the distribution diskette to
extract (uncompress) the distribution kit files.  (Run UNZIP on
EXE.ZIP and EXAMPLES.ZIP, and other ZIP files if included; e.g.,
UNZIP EXE.ZIP)An example of steps 2-5 would be:

cd \

mkdir veriwell

copy a:*.*	unzip exe

unzip examples



Edit your AUTOEXEC.BAT fileInclude the target directory in the
PATH

(Optional) SET DOS4GVM=1 (This enables virtual memory) 



Ensure that FILES in CONFIG.SYS is set to 20 or higher.

Installing VeriWell for DOS

This section describes in detail the procedure steps you must
follow to successfully install VeriWell on your PC.

Step 1.	Install the Hardware Key.

To install the hardware key on your PC, follow these steps.  You
must install the hardware key to use VeriWell (unless using
VeriWell/Free).  Figure 1 illustrates a and b.

a.	Attach one end of the key to a parallel printer port.  It
does not matter which.  Hardware keys can also be connected
together if there is more than one.

b.	Attach the printer cable to the other end of the key.



					Male DB-25 pin connector											(connect to PC's
parallel printer port)

					Female-DB pin connector (connect printer cable)

Figure 1:  Attaching the Hardware Key to a Parallel Printer Port

The use of the hardware key allows you to move VeriWell from PC
to PC making for easy portability of the software. 

Note:	When moving the hardware key from one PC to another to use
VeriWell, you must install the key before you invoke VeriWell. 
Do not remove the key while VeriWell is running.





Attaching the hardware key to your PC parallel printer port does
not deny your use of the port.  After attaching one end of the
key to the port, you can connect the printer cable to the other
end of the hardware key.

Step 2.	Create the Target Directory on Your PC's Hard Disk.

a.	At the DOS prompt, change drives to the hard disk on which
you intend to install VeriWell.  For example, if your hard disk
is Drive C, enter the following:

		>C:<return>

b.	Change directories to the hard disk's ROOT directory.  Enter
the following:

		C:>CD \<return>

c.	Use MKDIR command to create the target directory

		C:>MKDIR directory name<return>

	where directory name is the name you choose for the target
directory.  For example, if you choose the name VERIWELL for
your target directory, you would enter:

		C:>MKDIR VERIWELL<return>

d.	Change directories to the target directory

		C:>cd directory name<return>

	where directory name is the name you specify for the target
directory.

Step 3.	Copy files From the Distribution Diskette.

To copy files from the distribution diskette to the target
directory, follow these steps:

a.	Insert the distribution diskette into Drive A, then use the
COPY command to copy the files to the target directory.  Enter
the following:

		C:>COPY A:*.*<return>

b.	After pressing the return key, copy the distribution kit
files into the target directory.

c.	Eject the distribution diskette from Drive A

Step 4.	Back Up the Distribution Diskette Files.

To create a backup copy of the distribution kit files, complete
these procedures:

a.	Insert a blank, formatted diskette into Drive A, then use the
COPY command to copy files from the target directory to the
backup diskette.  For example, if your target directory is named
VERIWELL, you would enter:

		C:>COPY \VERIWELL\*.* A:<return>

	The command then copies the compressed distribution kit files
and the utility to uncompress them onto the diskette in Drive A.

b.	Remove the backup diskette from Drive A.  Store it in a safe
place.

Step 5.	Extract the Distribution Kit Files.

a.	Run UNZIP on each of the files with a .ZIP extension:

		C:>UNZIP EXE.ZIP



Installation is complete and VeriWell for DOS is now ready to
run.

About the DOS Extender

VeriWell for DOS is shipped with a DOS extender, DOS/4GW, from
Rational Systems, Inc.  To use the DOS Extender, DOS/4GW must be
invoked first.  DOS/4GW puts the system into protected mode (DOS
normally uses REAL -- 8086 emulation -- mode) and, optionally,
sets up paging.  The on-line file, DOS4GW.DOC, included with
your distribution media, provides detailed information on
configuring DOS/4GW through the use of environmental variables.

The executable file, dos4gw.exe, also included with your
distribution media, expects as its first argument the DOS
application that requires it, in this case veriwell.exe. 
Additional command line arguments apply to the veriwell.exe
application.  For example:

DOS4GW veriwell cpu.v

To simplify matters, veriwell.exe can be run without explicitly
invoking DOS4GW at the command line.  When veriwell.exe is run,
it will look for and execute dos4gw.exe first.  For this to work
properly, dos4gw.exe must be either in the path, or in the same
directory as veriwell.exe.

DOS Considerations

There are several aspects of using Verilog under DOS that are
not relevant under other environments.  These have to do with
memory display and interaction.

Memory

VeriWell uses a DOS extender which gives it the ability to
access all the memory in the system.  To enable page swapping,
set the environment variable, DOS4GVM, to 1 (e.g. set
DOS4GVM=1).  For more information and options regarding the
memory manager, see the on-line file on the distribution disk.

Beyond the memory used to compile a Verilog model, little
additional memory is used during runtime.  Once the model is
compiled and is running, the only additional memory that is used
is during the processing of interactive statements. 
Non-blocking assignments with delays use some memory during
processing and will return it after completion.

Scrolling and Shelling

DOS does not provide a windowing environment, yet the
development of Verilog models is greatly eased in a windowing
environment.  Specifically, it is often helpful to have an
active Verilog window alongside an editor window in which to
view the code and make changes when necessary.  Also, it is
generally desirable to run Verilog in a scrollable window.  Both
of these issues have been addressed by VeriWell.

VeriWell provides the ability to execute an external command and
to shell out to DOS at the VeriWell command line.  A single
exclamation mark ('!') followed by a command line will execute
that command in a DOS shell. For example: 

"!freemacs model.v".

A single exclamation mark by itself will open a DOS shell.

We recommend running VeriWell for DOS in an environment that
supports multiple DOS windows, such as OS/2 or Windows.

Control-D to Exit

Like UNIX-based tools, control-D can be used to exit VeriWell. 
But, unlike UNIX-based tools, the control-D must be followed by
a carriage return.

43 and 50 Lines per Screen

Three utilities are provided with the distribution media to
produce smaller screen font sizes so that more output is visible
at one time.  The utilities 43.com and 50.com produce screen
fonts that allow 43 and 50 lines on the screen, respectively. 
The utility 25.com restores the  font size to the normal size. 
Each of the font's sizes is the same width, that is, 80
characters per line.

Control-C and Control-Break

DOS senses that a control-C has been pressed only if it is the
first character in DOS's keyboard buffer.  If another key is
pressed, perhaps accidentally, before the control-C is pressed,
then DOS does not recognize it.  This may give the impression
that the system is hung.  Pressing control-Break is always
detected by DOS, so, if control-C does not work, always try
control-Break.

Positioning of Caps Lock and Control Keys

Most PC keyboards have the Caps Lock key and the Control key in
the opposite position than most Sun workstations.  Seasoned Sun
users may be unaccustomed to the position of these keys on a PC.
 Several programs are available that reverse the position of
these keys on the PC.  Wellspring Solutions, Inc. will provide
such a program at no cost upon request.

Line Terminators

Text files in DOS use a different line terminator than text
files in UNIX.  In DOS, lines end with a carriage return/line
feed combination.  In UNIX, lines end with only the line feed.

When transferring Verilog files (or any other text files) from
DOS to UNIX and UNIX to DOS, the carriage return must be
stripped or added.  This can be done in most editors using
global search-and-replace functions.  Also, there are two
utilities included with the distribution for doing this:
dtou.exe converts a DOS text file to UNIX format and utod.exe
converts a UNIX text file to DOS format.

Simulation Time Information

The system tasks $stop(2) and $finish(2) display time and memory
information.  The time information is based on wall-clock,
rather than actual CPU,  time.  The clock is paused while
waiting for interactive commands, but is not paused for other
interruptions, such as hitting control-S.Chapter 2:	VeriWell for Sparc

Overview

This chapter describes the system prerequisites you must meet
and the procedures you must follow to install and use VeriWell
successfully on your Sparc.

System Requirements

VeriWell for Sparc requires:

Sparc and Sparc compatible systems using SunOS 4.0.x or greater
(including Solaris versions)

8MB RAM, 2MB disk space

What is Included

The contents of the files included with VeriWell for Sparc are
described in your distribution media.  VeriWell may be
distributed in several ways.  If you received the software
electronically (BBS, FTP, Email), then, most likely, all of the
files are compressed into a single tared and compressed file.

Installing VeriWell for Sparc

This section describes the procedures you must follow to
successfully install VeriWell on your Sparc or Sparc-compatible
workstation.

Step 1.	Unarchive the VeriWell Distribution disk:

a.	% cd <VeriWell-directory>

b.	% tar xvf <disk-device>

Step 2.	Add:

	<VeriWell-directory> to your PATH 

	That is, edit your .login, .cshrc, or the appropriate file so
that the PATH variable also points to the VeriWell directory.

Installation is complete and VeriWell for Sparc is now ready to
run.

Sparc/UNIX Considerations

There are a few aspects of using VeriWell on a Sparc workstation
that are not relevant under other environments.  These have to
do with line terminators and the use of passwords.

Line Terminators

Text files in UNIX use a different line terminator than text
files in DOS.  In DOS, lines end with a carriage return/line
feed combination.  In UNIX, lines end with only the line feed.

When transferring Verilog files (or any other text files) from
DOS to UNIX and UNIX to DOS, the carriage return must be
stripped or added.  This can be done in most editors using
global search-and-replace functions.  Also, there are two
utilities included with the distribution for doing this:
dtou.exe converts a DOS text file to UNIX format and utod.exe
converts a UNIX text file to DOS format.

Passwords	

VeriWell on Sparc is password protected on a node-locked basis. 
The password is in the form of an 8-bit hex number.  The
password is unique for each hostid.  To invoke VeriWell with the
password, type:

veriwell -p12345678 ...

or

veriwell -f <passfile> ...

where <passfile> is a file in the form of:

-p12345678 // password for hostid 1234cdef

-p9abcdef  // password for hostid cdef1234...

The command line can be made less verbose by the use of aliases.
 For example:

alias ver veriwell -f /veriwell/passwdChapter 3:	VeriWell for Macintosh and Windows

Overview

VeriWell for Windows and VeriWell for Macintosh use a graphical
front-end to easily control the simulation and debugging of
VeriWell models.  This allows for integrated editing and
modification of Verilog models and the support of "projects"
which are collections of files comprising a particular model.

The interfaces for both Windows and Macintosh versions are
nearly identical and are therefore described together in this
section.  Where there are differences between the interfaces,
they are explicitly mentioned.

Before You Begin

Make sure you have a blank, formatted high-density diskette to
make a backup copy of your software.

System Requirements for Macintosh

VeriWell for Macintosh requires:

68020-based Macintosh or greater

4MB of memory and 2MB of disk space

We recommended that a processor cache be installed
Note:	VeriWell has been tested with System 7.1 but will most
likely work with later. versions.   



System Requirements for Windows

VeriWell for Windows requires:

386SX or greater IBM-compatible PC and Microsoft Windows 3.1 (or
Windows for Workgroups), or Microsoft Windows NT 3.1 or 3.5, or
OS/2 Warp 3.0

Microsoft's Win32s library (Windows 3.1 only)

At least 4MB of memory, 4MB of disk space (preferably
8MB)Note:	It is necessary that the Win32 extensions be installed
under Windows 3.x.  The Readme included with the Win32
extensions describes how to install the extensions.





What is Included

VeriWell for Macintosh distribution media consists of the
executable file, documentation files, and some example files. 
All of the files are packaged in a single self-extracting
executable file.

VeriWell for Windows distribution media consists of the VeriWell
software, documentation files, and some example files packaged
in one, compressed file, and the Win32s library2, which is
packaged separately in a single self-extracting executable file.

VeriWell for Macintosh and Windows is distributed in one of two
ways: by floppy disk or by electronic transfer through File
Transfer Protocol (FTP), through our Bulletin Board Service
(BBS), or by Email.

Installing VeriWell for Macintosh

These are the steps to follow to successfully install the floppy
disk.

Step 1.	Insert the Floppy into the Drive.

Step 2.	Drag the Self-extracting Application to a Folder on the
Hard Disk.

Step 3.	Double-click the Application.

This creates a folder and places all the distribution files in
it.

Installation is complete and VeriWell for Macintosh is now ready
to run.

VeriWell for Windows Installation Summary

A summary of the steps you must follow to install VeriWell for
Windows successfully appears below.  The section that follows
the summary, Installing VeriWell for Windows, describes the
procedures you must perform to complete each step.

Attach the hardware key to your PC's parallel printer port. 

Create a target directory for the VeriWell files, and, if
necessary, create a target directory for the Win32s library.

Copy the entire contents of the VeriWell distribution media to
its target directory.  Copy the Win32s library contents to its
target directory.

Make a backup copy of the distribution files by copying the
contents of each target directory onto a blank diskette.

Use the UNZIP utility provided for VeriWell, and run the Win32s
executable, to extract (uncompress) each set of distribution kit
files.

Install the Win32s software.

Install the VeriWell for Windows software.

Edit your AUTOEXEC.BAT file.

Ensure that FILES in CONFIG.SYS is set to 20 or higher.

Installing VeriWell for Windows

These are the steps to successfully install the floppy disk.

Step 1.	Attach the Hardware Key.

As with VeriWell for DOS, the registered VeriWell for Windows
uses a hardware key to enable the software.  Reference Part IV,
Chapter 1, in the section titled Installing VeriWell for DOS,
and its applicable notes, for complete instructions on
installing the hardware key on the printer port of your PC.  The
hardware key is plugged into a printer port of the system.  A
printer can be connected to the other side of the key.  The
existence of the key is transparent to all printer operations.

If VeriWell is invoked without the key, it will still run, but
with certain limitations.  These limitations are described in a
text file that is included with the distribution. 
TheVeriWell/Free version, readily available through FTP, BBS, or
by mail, is used without the hardware key as a teaching tool for
learning Verilog or for running small simulations.

Step 2.	Create the Target Directories on Your PC's Hard Disk.

The Microsoft Win32s library allows you to run Win32-based
applications on Windows 3.1.  If you are using VeriWell on
Windows, version 3.1, or Windows for Workgroups versions 3.1 or
later, and you do not already have Win32s installed on your
system, then you will need to create two separate target
directories; one for VeriWell and one for the Win32s library. 
For each of the target directories you create follow steps a, b,
c, and d.

a.	At the DOS prompt, change drives to the hard disk on which
you intend to install VeriWell.  For example, if your hard disk
is Drive C, enter the following:

		>C:<return>

b.	Change directories to the hard disk's ROOT directory.  Enter
the following:

		C:>CD \<return>

c.	Use MKDIR command to create the target directory

		C:>MKDIR directory name<return>

	where directory name is the name you choose for the target
directory.  For example, if you choose the name VERIWELL for
your target directory, you would enter:

		C:>MKDIR VERIWELL<return>

	If you choose the name WIN32S for your target directory, you
would enter:

		C:>MKDIR WIN32S<return>

d.	Change directories to the target directory

		C:>cd directory name<return>

	where directory name is the name you specify for the target
directory.

Step 3.	Copy files From the Distribution Diskette.

To copy files from the distribution diskette to each of your
target directories, follow these steps:

a.	Insert the distribution diskette into Drive A, then use the
COPY command to copy the files to the target directory.  Enter
the following:

		C:>COPY A:*.*<return>

b.	After pressing the return key, copy the distribution kit
files into the target directory.

c.	Eject the distribution diskette from Drive A.

Step 4.	Back Up the Distribution Diskette Files.

To create a backup copy of the distribution kit files, complete
these procedures:

a.	Insert a blank, formatted diskette into Drive A.  At the DOS
prompt, use the COPY command to copy files from each of your
target directories to a backup diskette.  For example, if your
target directory is named VERIWELL, you would enter:

		C:>COPY \VERIWELL\*.* A:<return>

	The command then copies the compressed files and the utility to
uncompress them (or the self-extracting executable file) onto
the diskette in Drive A.

b.	Remove the backup diskette from Drive A.  Store it in a safe
place.

Step 5.	Extract the Distribution Kit Files

a.	At the DOS prompt, in your VeriWell target directory, use an
'unzipper', such as PKUNZIP version 2.x, or UNZIP, to extract
each of the compressed files with a .ZIP extension.  The utility
UNZIP is included on your distribution media.

		C:>UNZIP EXE.ZIP

b.	At the DOS prompt, in your Win32s target directory, run the
Win32s executable file by typing the name of the file without
the .EXE extension at the command prompt.  For example:

		C:>W32S120

	This decompresses the Win32s files into an installation layout
(setup program) in your target directory

Step 6.	Install the Win32s Library	

If you are installing VeriWell to Windows 3.x, make sure at this
point in the VeriWell for Windows installation procedure that
you have the Win32s library installed.  Following is the
procedure.

a.	Start WindowsNote:	You will be alerted that file-sharing must
be enabled.  Run share.exe before starting Windows or add
share.exe to your autoexec.bat file.



b.	Select File|Run.  Browse for the setup.exe file in the target
directory you created for the Win32s library.  Initialize Win32s
setup by double-clicking on the setup.exe file.  The setup
program automatically installs Win32s.

c.	Press the continue button to install the Microsoft 'Freecell'
game that verifies the correct install if Win32s, or,

d.	Press the exit button to restart Windows without installing
Freecell.

e.	After successful installation, you may safely delete the
Win32s target directory and its contents.

Step 7.	Install VeriWell for Windows.

a.	Start Windows.

b.	Select File|New menu item and create a New Group by pressing
the Program Group button.  In the description box, give this New
Group any name you wish, for example, VeriWell. Click OK.  A new
window group will be created called VeriWell.

c.	Create the VeriWell icon by again selecting the File|New menu
item and pressing the Program Item button.  Type in the path of
the target directory where you extracted the VeriWell files, or,
use the browse button to find the path.  Click OK.  A new item
(icon) will appear in the new VeriWell window.

Step 8.	Edit your AUTOEXEC.BAT file to include the target
directory in the PATH

Step 9.	Set the files in config.sys to 20 or higher.



The installation procedures for VeriWell for Windows and Win32s
are complete and VeriWell is now ready to run.

Quick Start

VeriWell for Windows and Veriwell for Macintosh both utilize a
graphical user interface.  This makes setting up simulations
with many files and many options simpler to manage.  However,
all of the standard command file options are available and, in
fact, even command files and input files are supported.

Working with Projects	

For each module, there is a "project".  The project is the
collection of source files and options that are required to run
the simulation.

To simulate a module, first open a new project (Project|New), ...

Project Definition

A project keeps track of all the source files and stores
information needed to debug, compile, and create the program..
The following section explains how to create a new project, open
or close and existing project, and add, rearrange, or remove
files.

The Project Window

The project window displays the text documents in your project. 
Figure 1 shows a project window.  It lists the names of the text
documents to be compiled and simulated.





Figure 1

The project window can be resized by the grow box found at the
bottom right corner.  The project window can also be enlarged by
the zoom box found at the top right corner.Creating a New Project

To create a new project, use New project...command from the
Project menu.  You will see a standard dialog box, like Figure
2.  To create a project file, simply type in the name and click
Save.  You can also create a new folder for your project by
clicking on New Folder button.





Figure 2

Opening an Existing Project

To open an existing project, double-click on its icon from the
Finder or use the Open project ... command in the Project menu. 
You will see a dialog box similar to Figure 3.







Figure 3

Note:	You can have only one project document open at a time.





Closing Projects

Use the Close Project command in the project Menu to close the
project document.  Any text documents that are open will remain
open.

Adding Files to Projects

There are two methods for adding files to a project.  

If you are editing a text document that is not included in the
project window, use the Add command in the Project Menu.  This
allows you to add the file in the current edit window to the
project.

If it is a new file, you must save it with Save As ... before
you can add it to the project.

To add a file on disk to a project, choose the Add Files ...
command in the Project Menu.  You'll see the dialog box as in
Figure 4.  Only one file at a time may be selected to be added
to the project.  Click on the file you wish to add and choose
Open.





						Figure 4

When a file is added to the project list, it is appended to the
list.  The files are compiled in the order listed.  If the file
name is too long for the project window, it will be shortened to
fit.  The file names are separated by a dotted line as shown in
Figure 5.  To rearrange the list, select a file name and drag it
to the position you wish by using the mouse.



						Figure 5



Removing Files from the Project

To remove a file from a project, select a file in the project
window and choose Remove a File command from the Project Menu. 
This command only removes the file from the open project and
will not delete the file from your disk.

Changing Project Preferences

To change any of the preferences for an opened project, select
Preference and Project from the Edit ZMenu.  Figure 6 is an
example of the project preference dialog box.



	

						Figure 6

You can change the font type and size for the project list by
using the pop-up menus.

To enable tracing, check the Trace On check box.  When the
simulation is run, every statement executed will produce a text
output showing the file name and line number containing it.

To enable a synopsis checking, check the Synopsis Checking check
box.

To pause for input before running a simulation, check the Prompt
Before Running check box.

To enable a key file, check the Key File check box.  When
running a simulation, every command entered will be written into
the key file.  The default key file is VeriWell.key.

To specify a key file, type the path name into the text box or
use the Select button to choose a key file by using a file
selection dialog box.

To enable the log file, check the Log File check box.  When the
simulation is running, output from the console window will be
appended to the log file.  The default log file is VeriWell.log.
 To specify a log file, type the path name into the text box or
use the Select button to choose a log file using a selection
dialog box.

The Output Directory specifies the default folder where the
VeriWell simulator will create output files.  If the default
folder is not specified, output files will be created in the
folder containing the currently opened project file.  To specify
an output directory, use the Select button to choose a folder. 
You can also type the path name directly into the text box.

The Use Defaults button will set all the project preferences to
match the VeriWell application defaults.

The Set Defaults button will set the VeriWell application
defaults to match those currently displayed in the dialog box.

The Cancel button will discard any changes made in the project
preferences window.

The OK button will change the project preferences.

Editing Files

Creating and Opening Files

To open or create a new file, you need not have a project open. 
You can open as many files as the memory in your Macintosh
allows, and each file appears in its own edit window.

Creating a New File

To create a new file, choose New from the File Menu.  An
untitled edit window appears as shown below in Figure 7.  The
cursor appears in the top left corner ready for typing.





Figure 7



Opening a Text File

There are two methods for opening saved files.

The Open ... command in the File menu opens any text document. 
A dialog box displays the names of all the text files in the
current folder.  The file selected will appear in its own edit
window.

A second way to open a text file that is already in your project
is to double click on its name in the project window.  If the
file is already open, then double clicking on its name will
bring the file's edit window to the front for editing.  Under
the Windows Menu is a list of all opened text files and projects.

Editing a File

The editor for VeriWell employs all the standard Macintosh and
Windows editing techniques.  Double clicking on a word selects
the entire word and triple clicking anywhere in a line selects
the entire line.  Cut, Copy, Paste, and Undo all perform the
same functions as in other Macintosh and Windows applications. 
The function keys F1 - F4 as well as the Command shortcuts will
also work for cut, copy, paste, and undo.

Typing Text

The VeriWell editor does not have the word wrap feature as in
other editors.  If you type past the right edge of the window,
the window automatically scrolls horizontally so you will see
the inserting point.  You can use the horizontal scroll bar to
see the beginning of the line.

Undoing Changes to a File

You can use the Undo command from the Edit Menu to change the
last thing you did.  Undo will allow you to undo multiple
operations with a limit set in the Editor Preference Window. 
The wording of the Undo command will reflect the operation to be
undone.  If you have typed in a line, the command will read Undo
Typing.  If you do choose Undo, the command will now say Redo
Typing.  There are also two shortcuts for Undo; you can use
Command-Z or the F1 function key.  You can Revert to Saved under
the File Menu if you wish to undo all the changes to a text file.

Selecting Words and Lines

To select a word, double click on that word.  If you double
click on a word and drag the mouse, you can extend the selection
by word.  To extend an existing selection, hold down the Shift
key and click to the end of the new selection.  You can move an
existing selection by clicking in the selection while holding
the mouse down and dragging the selection.  You can also
duplicate a selection by clicking in the selection while holding
down the Option key and dragging the selection.  To select a
line, triple click on any point in that line.  To select the
whole file, choose Select All from the Edit Menu or use
Command-A.

Indenting

When you use Return to end a line, the editor indents the new
line with the same number of leading tabs and spaces as the
previous line.  Backspacing changes the indentation.  Tab
spacing can be changed through the Editor Preference Dialog Box.

Shifting Blocks Right and Left

You can change the indention level for a range of a line by
using the Shift Right and Shift Left commands in the Edit Menu. 
Shift Right inserts a tab at the beginning of each selected
line, while Shift Left will remove the leading tab from each
selected line.

Changing Editor Preferences

To change any of the editor window settings, select Preferences
and Editor under the Edit Menu.  Figure 8 is an example of the
Editor Preference dialog box.





Figure 8



The font type and size for the editor window can be changed by
using the pop-up menus.

The Tab Spacing can be changed by typing in a new number in the
Tab Spacing text box.

Undo depth allows you to set the limit for how many operations
can be undone.  As in tab spacing, a new number can be typed in
the Undo Depth text box.

The OK button changes the console preferences.

The Cancel button discards any changes made in the console
preference window.

The Use Defaults button sets all the console preferences to
match the VeriWell application defaults.

The Set Default button sets the VeriWell application defaults to
match those currently displayed in the dialog box.

Moving Around a File

The VeriWell editor allows you several ways to move around the
file quickly and efficiently.

Using Arrow and Function Keys

The arrow keys will move the cursor up, down, left, or right. 
At the end of a line, the right (or left) arrow key will go to
the beginning of the next line (or end of the previous line). 
If you have an Apple Extended Keyboard, you can use the keys
above the arrow keys as summarized below:

Press This 	To Get This 

Home 	Top of the file 

Page Up 	Back to previous screen 

Forward Del 	Deletes the next character 

End 	End of the file 

Page Down 	Forward to next screen 

Shift-Right Arrow 	Extends right selection by one character 

Shift-Left Arrow 	Extends left selection by one character 

Shift-Up Arrow 	Extends selection up by line 

Shift-Down Arrow 	Extends selection down by line 

Shift-Option- Right-Arrow 	Extends right selection by word 

Shift-Option-Left-Arrow 	Extends left selection by word 





The Home, End, Page Up, and Page Down will not move the
insertion point, but merely scroll the file.

Moving to a Specific Line

The Go To Line ... (or Command-) under the Search menu allows
you to move to a specific line in the file.  Lines are numbered
consecutively beginning with the number 1.  When you choose Go
to Line ... you will see the following dialog box, Figure 9.



   Figure 9



To go to a particular line, type in the line number and click
OK.  If you change your mind, you can click Cancel.  The editor
moves the insertion point to the beginning of the line you have
chosen.  While in the console window, you can triple click on an
error or trace message to go to a particular line.

Saving a File

It is always a good idea to save your work periodically.  To
save a file without closing the file, you can use the Save
command from the File menu or use Command-S.  If the file has
not been saved before, you will be asked to name the file. 
Under the Window menu, there is a list of all opened text files.
 If a diamond appears before the file name, then changes have
been made since the last time a Save has occurred.

Saving A File with a Different Name

The Save As ... command will ask you to name a new file and then
saves the contents of the edit window under that name.

Saving all Open Files

To save all the open text files, use Save All from the Window
menu.  This command works the same as saving each file
individually.

Searching and Replacing Text

The VeriWell editor allows you a variety of options for
searching and replacing text within a file.

Find a String

Use the Find ... command in the Search menu when you want to
find a string or type Command-F.  You will see the following
dialog box, Figure 10.





Figure 10



Type the string you are looking for in the Search For file and
click on the Find button.  The editor will highlight the text if
the string appears in the file.  If it does not appear, the
editor will beep.  When the Ignore Case option is checked, the
editor will match the search string regardless of case.  To find
the next instance of the string, use the Find Again command or
type Command-G.  The search will only look in the active text
file and not in all the text files of the project.

The Enter Selection command from the Search menu allows you to
set the search string from the active window.  If you highlight
the search string in the active window, you can use the Enter
Selection to place the string into the Find dialog box.  You can
then use Find Again to begin searching.

Replacing a String

If you would like to replace some but not all occurrences of the
search string, enter a replacement string in the Replace field
of the Find ... dialog box.  When the editor highlights the
first instance, you can use one of the following commands:

Find Again (or Command-G) to find the next occurrence of the
search string

Replace (or Command-=) to replace the search string with a
replacement string

Replace & Find Again (or Command-H) to replace the current
string and then immediately go on to the next one

Replace All is a global replace for the entire text file.  If
you do not type in a replacement string, the editor will delete
every occurrence of the search string.

Printing Files

To print the contents of the front most windows, choose Print
... from the File menu.  The standard printing dialog box will
appear.  You can print the contents of an editor window or
console window.

The file menu also contains a standard Page Setup ... command
that will allow you to set the page size and other options
before you print.

Closing a File

To close a file, click on the window's close box, choose the
Close command from the File menu, or use Command-W.  If you have
made any changes, the editor will ask you if you wish to save it
before closing.  The Close All command under the Window menu
closes all the open text files.  If the file has not been saved,
the editor will ask you if you wish to save it before closing.

VeriWell Console Window			

Opening

When you start VeriWell, the console window is opened
immediately and available for use.  The window can be hidden by
clicking in the close box of the window.  To have the console
window open again, select Console from the Window menu.  The
window will also be brought to the front if Run (Command-R) is
selected from the Project Window.  The latter method will only
work if a project is open.  Figure 11 is an example of an open
VeriWell Console Window.





Figure 11



Resizing

The console window can be resized by using the zoom and grow
boxes found in the right hand corners of the window.

Entering Commands

There are three ways to enter commands; by Project menu, by the
buttons found at the bottom of the console window, or by typing
commands into the Console Window.

Entering Commands Using the Menu or Button Commands

The following is a brief description of menu or button commands:

Run 	Start a compilation or simulation 

 Restart 	Restart a compilation or simulation 

 Continue 	Continue simulation 

 Stop 	Stop simulation 

 Exit 	Exit simulator 

 Step 	Advances simulator one time step 

 Trace 	Advances simulator one time step and traces line 
executed 



The buttons will work exactly as the menu commands but Run and 
Restart are on the same button.  The buttons will also appear 3D
at times when these commands are legal.

Entering Commands into the Console Window

To enter a command into the console window, type the command in
the window and Return.  You can copy and paste text from the
clipboard.  The text will be pasted at the bottom of the window.
 By using the return key, the text will be executed.

Console Output

The console will contain the output from the compilation and
simulation of the project.  By triple clicking on an error
message, the file containing the error will be opened with the
error line highlighted.  When tracing during a simulation,
triple clicking on a trace line will take you to the file and
highlight the line being traced.

Searching

In the console window, VeriWell permits searching for text.

Finding a String

Use the Find ... command in the Search menu when you want to
find a string or type Command-F.  Type the string you are
looking for in the Search For field and click on the Find
button.  If the string appears in the console window, it will be
highlighted.  If it does not appear, the editor will beep.

If you wish to find the next instance of the string, use the
Find Again command in the Search menu or type Command-G.  When
the Ignore Case option is checked, the editor will match the
search string regardless of case.

The Enter Selection command from the Search menu allows you to
set the search string from the active window.  If you highlight
the search string in the active window, you can use the Enter
Selection to place the string into the Find dialog box.  You can
then use Find Again to begin searching.

Printing

To print the entire contents of a console window, choose Print
... from the File menu.  The standard printing dialog box will
appear.  The File menu also contains a standard Page Setup ...
command that will allow you to set the page size and other
options before you print.

Running a Simulation

When the Run command is chosen, the program will begin running
the files in a project.  If there are any files that are not up
to date, a prompt box will appear.  If you select Yes, the
modified files will be saved before the run is started.  If you
choose No, the files will not be saved, but the current
displayed versions of the files will be compiled.  If you choose
Cancel, no simulation will be run.  You have this option for
each modified file.

Changing Console Preferences

To change the preferences of the console window, you can choose
Preferences and Console from the Edit menu.  You will see the
following dialog box, Figure 12.





Figure 12



The font type and size for the console window can be changed by
using the pop-up menus.

If you want the console clear before beginning the run, check
the Clear-On Run check box.

The console window keeps a history of the data that has been
outputted.  VeriWell allows you to scroll back to view this
data, but this amount data is limited.  When it has reached its
limit, characters at the beginning of the window are deleted. 
In this preference window, you can set the Console Buffer Size
(bytes).

The OK button will change the console preference.

The Cancel button will discard any changes made in the console
preference window.

The Use Defaults button will set all the console preferences to
match the VeriWell application defaults.

The Set Defaults button will set the VeriWell application
defaults to match those currently displayed in the dialog box.

Closing

To close the console window, click on the window's close box.

Search List Window

VeriWell allows each project to specify a set of folders to
search for files opened by the VeriWell simulator.  The search
list window is used to add and delete directories from this
list.  The window also allows the order of searching to be
controlled.  This search list information is saved with each
VeriWell project and will be restored whenever the project is
opened.

Opening

The search list window is opened by selecting the Search List
... command from the Edit menu.  This window is allowed to be
opened only when a project is opened.  When the Search List ...
command is executed, the Search List window is opened.  See
Figure 13.





Figure 13



The first entry of the search list window always contains an
absolute pathname referencing the location of the currently
opened project file.  This entry cannot be deleted or edited. 
The folder is always the first location searched for any file to
be opened by the VeriWell simulator.

Adding New Paths

Additional folders can be added by selecting the Add Path button
in the lower left of the search list window.  When this button
is clicked, a dialog window will be presented allowing a new
folder to be selected to be added to the list.  To select a new
folder, navigate to the folder to be added and then click on the
Search Here button.  This new folder will always be added to the
end of the list.





Figure 14



Folder Search Order

The order the VeriWell simulator uses to search folders is the
same as the order the folders are listed in the Search List
Window.  The first folder listed is the first folder to be
searched.  The last folder listed is the last to be searched.

Changing the Search List Order

The Search List Window can be used to change the order that the
folders are searched.  An entry in the list may be dragged to
the desired location in the list by selecting the entry with the
mouse, holding the button down and dragging the item to the
desired location in the list.  When the button is released, this
item will be moved to the highlighted location and the rest of
the list will be moved down.

Absolute versus Relative References

The folders to be searched will be saved in the project file
when it is closed.  The folders' locations may be saved either
as absolute references or as project relative references. 
Absolute references specify the disk the folder is on and
complete path to the folder to be searched.  Project relative
references are stored by referencing the folder, starting at the
folder containing the project.  Relative references must reside
on the same disk as the currently opened project.  

The advantage of relative references is that if the project and
its associated folders to be searched are all contained in a
common folder and that folder is moved to another machine or
disk, the search paths all remain valid.  Sometimes this is not
desired, such as a folder containing a library of files that is
always in a fixed place, and in this case, absolute references
should be used.

When new paths are added, and they are on the same disk volume
as the currently opened project, they will always be added as
project relative references.  Otherwise they are added as
absolute references.  

The  folders listed in the Search List Window may be changed
between absolute and relative references by selecting the folder
in the list with the mouse and then clicking on the
Absolute/Relative button.  If any item is double clicked, it
will be toggled between absolute and relative references mode.

Removing Paths

Folders may be removed from the Search List Window by selecting
the folder in the list using the mouse and then clicking on the
Remove Path button.

Resizing

The search list window can be resized by using the zoom and grow
boxes found in the right hand corners of the window.

Closing

To close the Search List Window, click on the window's close box.

Veriwell Menus

Apple (VeriWell for Macintosh)

About VeriWell for Mac...



This command will inform you of the version of VeriWell.  When
this command is selected, a dialog window is displayed with
information about VeriWell.  Clicking anywhere in the window
will cause it to close.

File





Figure 15

New

This command will open a new untitled window.  This file must be
saved if you intend to add it to a project list.

Open...

This command will display a file selection dialog box allowing
any text file to be opened and edited.  A file that is in the
currently opened project file list may also be opened by double
clicking on the name in the project list window.

Close

This command will close the currently active window.  It
performs the same function as clicking in the window close box. 
If you try to close a file and it has been modified you will be
prompted with a dialog box asking whether you would like to save
the changes, discard them, or cancel the Close command.

Save

This command will save the active window to disk.  If the window
is currently untitled, you will be prompted to name the file.

Save As...

This command lets you save the active window under a different
name.  The contents of the original file will remain unchanged.

Revert to Saved

This command will discard any changes made to the active window,
restoring it to the last saved version.

Page Setup...

This command will open the standard Page Setup ... dialog box. 
This allows the selection of paper size and orientation.

Print...

This command will open the standard Print ... dialog box
allowing the specification of the number of pages and copies to
be printed.  Printing may be canceled by typing Command-Period.

Quit ('Exit' in VeriWell for Windows)

This command exits VerWell and returns to the Finder.

Edit							

   	

Figure 16

Undo

This command will undo the last command.  VeriWell supports
multiple levels.  The number of levels maintained is
configurable through the Editor Preference Window.

Redo

This command will redo the last undone command.  VeriWell
supports multiple levels.  The number of levels maintained is
configurable through the Editor Preference Window.

Cut

This command will delete the currently selected text to the
clipboard.

Paste

This command will copy the contents of the clipboard and insert
it into the active window at the current insertion point.

Clear

This command will delete the currently selected text.

Select All

This command will select all text in the active window.

Shift Left

This command will shift the currently selected lines to the left
by one tab space.

Shift Right

This command will delete the first character of the currently
selected lines if they begin with a tab.

Preferences -> Project...

This command will display the Project Preference Dialog.  This
allows the project preferences to be modified.

Preferences -> Editor...

This command will display the Editor Preference Dialog.  This
allows the editor preferences to be modified.

Preferences -> Console...

This command will display the Console Preference Dialog.  This
allows the console preferences to be modified.

Preferences -> Apply Defaults

This command will set the current project preferences to match
the VeriWell application default preferences.

Preferences -> Restore Defaults

This command will restore the VeriWell application default
preferences to their factory settings.

Search List...

This command will open the Search List Window.  This command is
only available when a project is currently opened.

Search





Figure 17

Find...

This command will open a dialog box allowing the entry of a
search and a replace string.  When the OK button is clicked a
search is begun following the inserting point for text matching
the search string.  If a match is found the text will be
highlighted.

Enter Selection

This command will place the current text selection into the
search string.

Find Again

This command will find the next occurrence of the search string.
 If a match is found it will be highlighted.

Replace

This command will replace the current selection with the
contents of the replace string.

Replace And Find Again

This command will replace the current selection with the
contents of the replace string, finds the next occurrence of the
search string but does not replace it.

Replace All

This command will replace all occurrences of the search string
with the replace string.

Go To Line...

This command will prompt for a line number.  The current window
will scroll to that line and select it.

Project





Figure 18

New Project...

This command will create a new project.  You will be prompted
for a name for this project.  The project, editor, and console
preferences will be set to the VeriWell application default's
preferences.

Open Project...

This command will open a previously created project.  You will
be prompted to select a project file.

Close Project

This command will close the currently opened project.

Add Files...

This command will display a file selection dialog box.  The
selected file will be added to the end of the opened project
file list.

Remove File

This command will remove the currently selected file from the
project list.

Add

This command will add the active window to the project file list.

Run

This command will compile and run the currently opened project.

Restart

This command will terminate the current selection, recompile,
and run it.  It is equivalent to interrupting the simulation,
entering the '$finish;' command and issuing the Run command.

Exit

This command will terminate the current simulation.  It is
equivalent to interrupting the simulation and entering the
'$finish;' command.

Stop

This command will interrupt the current simulation.  It is
equivalent to typing a Command-Period.  Once the simulation is
interrupted the user will be prompted for input.

Continue

This command will continue the simulation from the point it was
interrupted.  This command is equivalent to typing a '.' command.

Step

This command will execute the next statement and return control
to the user.  This command is equivalent to typing a ';' command.

Trace ('Step and Step Trace' in VeriWell for Windows)

This command will execute the next statement, printing out a
list of all simulation activity associated with the statement. 
Control will then be returned to the user.  This command is
equivalent to typing a ',' command.

Windows (VeriWell for Macintosh)



Figure 19a

Save All

This command will save the contents of all unsaved, modified
text files.

Close All

This command will close all opened text windows.

Console

This command will make the Console Window visible and the front
most window.

Project Window

This command will make the currently opened project window the
front most window.

Edit Windows

There will be one menu item for each opened text window.  The
selection of these menu items will cause the corresponding
window to be brought to the front.

Window (VeriWell for Windows)



Figure 19b

Cascade

This command arranges windows in an overlapping fashion.

Tile

This command arranges windows next to each other.

Arrange Icons

This command places icons in a neat row.

Edit Windows

There will be one menu item for each opened text window.  The
selection of these menu items will cause the corresponding
window to be brought to the front.

Help (VeriWell for Windows)





Figure 20

Contents

This command lists the entire contents of the Help file; the
Introduction to 'VeriWell Basics', the 'How To' list and the
'Commands and Buttons' list.

Search for Help on...

The 'Search for...' command allows you to type in a word you are
searching for or select a word or phrase from a list.  You can
also select and 'Go To' topics.

How to Use Help

If you are new to Help, choose 'Help Basics'.  You can also
choose a 'How To' topic from an alphabetical list or click on a
topic from the 'Commands and Buttons' list.

About VeriWell

This command will inform you of the version of VeriWell.  When
this command is selected, a dialog window is displayed with
information about VeriWell and Wellspring Solutions.  Clicking
anywhere in the window will cause it to close.

Command Shortcuts for Macintosh and Windows	

	

Command-N 	New - Create new text file 

Command-O 	Open - Open a text file 

Command-W 	Close - Close a text file 

Command-S 	Save - Save a text file 

Command-P 	Print - Print a text file 

Command-Q 	Quit - Exit VeriWell 

Command-X 	Cut - Cut selection and put in clipboard 

Command-C 	Copy - Copy current selection to clipboard 

Command-V 	Paste - Insert clipboard contents at selection 

Command-A 	Select All - Select all text 

Command-[ 	Shift Left - Shift selected lines one tab stop 

Command-] 	Shift Right - Shift selected lines right one tab stop 

Command-F 	Find - Search for text 

Command-E 	Enter selection - Enter selection into search field 

Command-G 	Find Again - Find next occurrence of search string 

Command-= 	Replace - Replace selection with replacement string 

Command-H 	Replace and Find Again - Replace selection and
replace next occurrence of search string 

Command-, 	Go To Line - Go to given line 

Command-R 	Run - Run simulation 

Command-. 	Stop - Interrupt simulation 

Command-0 	Console - Make console window visible and bring to
the front 

page up 	Scroll upward one page 

page down 	Scroll downward one page 

home 	Scroll to beginning 

end 	Scroll to end 

del 	Delete character after insertion point 

delete 	Delete character before insertion point 

Up arrow 	Move insertion point upward one line 

Down arrow 	Move insertion point downward one line 

Right arrow 	Move insertion point to the right one character 

Left arrow 	Move insertion point to the left one character 

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1 The continuous assignment represents one of possibly many
drivers to the net, foo; the net itself is scheduled for
updating for sometime later in the current simulation time unit.

2 Microsoft Win32s, version 1.20, is required to install and run
VeriWell on Windows 3.1.  The compressed Win32s file is packaged
separately as a self-extracting executable file.

